diff options
| author | Nathan Binkert <binkertn@umich.edu> | 2006-02-20 23:41:50 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2006-02-20 23:41:50 -0500 |
| commit | 3a0102536bdbf00629e6ba944bd55ee0ec77fb52 (patch) | |
| tree | 125bebe1771dbf336f7830a030ab39fc67ae9e9f /dev/sinicreg.hh | |
| parent | 7c642b710679f01d4ec43e6562dd854180dd8c41 (diff) | |
| download | gem5-3a0102536bdbf00629e6ba944bd55ee0ec77fb52.tar.xz | |
Get rid of the code that delays PIO write accesses
until the cache access occurs. The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
get rid of pio_delay write and the associated code to move
the write to the cache access function
dev/sinicreg.hh:
no more write delays
python/m5/objects/Ethernet.py:
get rid of pio_delay write
--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
Diffstat (limited to 'dev/sinicreg.hh')
| -rw-r--r-- | dev/sinicreg.hh | 40 |
1 files changed, 19 insertions, 21 deletions
diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index 343db6303..1378e079d 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -157,8 +157,6 @@ struct Info uint8_t size; bool read; bool write; - bool delay_read; - bool delay_write; const char *name; }; @@ -167,33 +165,33 @@ struct Info inline const Regs::Info& regInfo(TheISA::Addr daddr) { - static Regs::Info invalid = { 0, false, false, false, false, "invalid" }; + static Regs::Info invalid = { 0, false, false, "invalid" }; static Regs::Info info [] = { - { 4, true, true, false, false, "Config" }, - { 4, false, true, false, false, "Command" }, - { 4, true, true, false, false, "IntrStatus" }, - { 4, true, true, false, false, "IntrMask" }, - { 4, true, false, false, false, "RxMaxCopy" }, - { 4, true, false, false, false, "TxMaxCopy" }, - { 4, true, false, false, false, "RxMaxIntr" }, + { 4, true, true, "Config" }, + { 4, false, true, "Command" }, + { 4, true, true, "IntrStatus" }, + { 4, true, true, "IntrMask" }, + { 4, true, false, "RxMaxCopy" }, + { 4, true, false, "TxMaxCopy" }, + { 4, true, false, "RxMaxIntr" }, invalid, - { 4, true, false, false, false, "RxFifoSize" }, - { 4, true, false, false, false, "TxFifoSize" }, - { 4, true, false, false, false, "RxFifoMark" }, - { 4, true, false, false, false, "TxFifoMark" }, - { 8, true, true, false, true, "RxData" }, + { 4, true, false, "RxFifoSize" }, + { 4, true, false, "TxFifoSize" }, + { 4, true, false, "RxFifoMark" }, + { 4, true, false, "TxFifoMark" }, + { 8, true, true, "RxData" }, invalid, - { 8, true, false, false, false, "RxDone" }, + { 8, true, false, "RxDone" }, invalid, - { 8, true, false, false, false, "RxWait" }, + { 8, true, false, "RxWait" }, invalid, - { 8, true, true, false, true, "TxData" }, + { 8, true, true, "TxData" }, invalid, - { 8, true, false, false, false, "TxDone" }, + { 8, true, false, "TxDone" }, invalid, - { 8, true, false, false, false, "TxWait" }, + { 8, true, false, "TxWait" }, invalid, - { 8, true, false, false, false, "HwAddr" }, + { 8, true, false, "HwAddr" }, invalid, }; |