add support for delaying pio writes until the cache access occurs

dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d

1 files changed, 29 insertions, 19 deletions

diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh
index 12f545255..30f5b3c95 100644
--- a/dev/sinicreg.hh
+++ b/dev/sinicreg.hh
@@ -140,6 +140,8 @@ struct Info
     uint8_t size;
     bool read;
     bool write;
+    bool delay_read;
+    bool delay_write;
     const char *name;
 };
 
@@ -148,26 +150,34 @@ struct Info
 inline const Regs::Info&
 regInfo(Addr daddr)
 {
+    static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
     static Regs::Info info [] = {
-        { 4, true,  true,  "Config"     },
-        { 4, false, true,  "Command"    },
-        { 4, true,  true,  "IntrStatus" },
-        { 4, true,  true,  "IntrMask"   },
-        { 4, true,  false, "RxMaxCopy"  },
-        { 4, true,  false, "TxMaxCopy"  },
-        { 4, true,  false, "RxMaxIntr"  },
-        { 0, false, false, "invalid"    },
-        { 4, true,  false, "RxFifoSize" },
-        { 4, true,  false, "TxFifoSize" },
-        { 4, true,  false, "RxFifoMark" },
-        { 4, true,  false, "TxFifoMark" },
-        { 8, true,  true,  "RxData"     }, { 0, false, false, "invalid" },
-        { 8, true,  false, "RxDone"     }, { 0, false, false, "invalid" },
-        { 8, true,  false, "RxWait"     }, { 0, false, false, "invalid" },
-        { 8, true,  true,  "TxData"     }, { 0, false, false, "invalid" },
-        { 8, true,  false, "TxDone"     }, { 0, false, false, "invalid" },
-        { 8, true,  false, "TxWait"     }, { 0, false, false, "invalid" },
-        { 8, true,  false, "HwAddr"     }, { 0, false, false, "invalid" }
+        { 4, true,  true,  false, false, "Config"     },
+        { 4, false, true,  false, false, "Command"    },
+        { 4, true,  true,  false, false, "IntrStatus" },
+        { 4, true,  true,  false, false, "IntrMask"   },
+        { 4, true,  false, false, false, "RxMaxCopy"  },
+        { 4, true,  false, false, false, "TxMaxCopy"  },
+        { 4, true,  false, false, false, "RxMaxIntr"  },
+        invalid,
+        { 4, true,  false, false, false, "RxFifoSize" },
+        { 4, true,  false, false, false, "TxFifoSize" },
+        { 4, true,  false, false, false, "RxFifoMark" },
+        { 4, true,  false, false, false, "TxFifoMark" },
+        { 8, true,  true,  false, true,  "RxData"     },
+        invalid,
+        { 8, true,  false, false, false, "RxDone"     },
+        invalid,
+        { 8, true,  false, false, false, "RxWait"     },
+        invalid,
+        { 8, true,  true,  false, true,  "TxData"     },
+        invalid,
+        { 8, true,  false, false, false, "TxDone"     },
+        invalid,
+        { 8, true,  false, false, false, "TxWait"     },
+        invalid,
+        { 8, true,  false, false, false, "HwAddr"     },
+        invalid,
     };
 
     return info[daddr / 4];