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authorAli Saidi <saidi@eecs.umich.edu>2004-01-30 15:24:50 -0500
committerAli Saidi <saidi@eecs.umich.edu>2004-01-30 15:24:50 -0500
commit0035440536e4c275d73fd3bb516f46d0d2df1f6b (patch)
treeef2b57e4b49edc8b98f0172c09cc00d7d8ad7af5 /dev/tsunami.hh
parent00c49783ef406aaee227aff10624da9feeeb8ce8 (diff)
downloadgem5-0035440536e4c275d73fd3bb516f46d0d2df1f6b.tar.xz
Linux boots with no devices
dev/tsunami.hh: Started commenting code dev/tsunami_cchip.cc: removed unneccessary config files dev/tsunami_io.cc: Added code to see the value written dev/tsunami_uart.cc: conviently one of the addresses the SuperI/O southbridge can be is the same space as the UART. This stops the simulator from panicing although it should probably be changed a bit. --HG-- extra : convert_revision : a3334a2c418ee8228089d0e1791fa78bbb276fe5
Diffstat (limited to 'dev/tsunami.hh')
-rw-r--r--dev/tsunami.hh39
1 files changed, 38 insertions, 1 deletions
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 57e4b8991..e6623899d 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -26,6 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+/**
+ * @file
+ * Declaration of top level class for the Tsunami chipset. This class just retains pointers
+ * to all its children so the children can communicate
+ */
+
#ifndef __TSUNAMI_HH__
#define __TSUNAMI_HH__
@@ -39,29 +45,60 @@ class TlaserClock;
class EtherDev;
class TsunamiCChip;
class TsunamiPChip;
+class TsunamiPCIConfig;
+
+/**
+ * Top level class for Tsunami Chipset emulation.
+ * This structure just contains pointers to all the
+ * children so the children can commnicate to do the
+ * read work
+ */
class Tsunami : public SimObject
{
public:
+ /** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 4;
+ /** Pointer to the interrupt controller (used to post and ack interrupts on the CPU) */
IntrControl *intrctrl;
-// ConsoleListener *listener;
+ /** Pointer to the UART emulation code */
SimConsole *cons;
+ /** Pointer to the SCSI controller device */
ScsiController *scsi;
+ /** Pointer to the ethernet controller device */
EtherDev *ethernet;
+ /** Pointer to the Tsunami CChip.
+ * The chip contains some configuration information and
+ * all the interrupt mask and status registers
+ */
TsunamiCChip *cchip;
+
+ /** Pointer to the Tsunami PChip.
+ * The pchip is the interface to the PCI bus, in our case
+ * it does not have to do much.
+ */
TsunamiPChip *pchip;
+ /** Pointer to the Tsunami PCI Config Space
+ * The config space in tsunami all needs to return
+ * -1 if a device is not there.
+ */
+ TsunamiPCIConfig *pciconfig;
+
int intr_sum_type[Tsunami::Max_CPUs];
int ipi_pending[Tsunami::Max_CPUs];
int interrupt_frequency;
public:
+ /**
+ * Constructor for the Tsunami Class.
+ * @param
+ */
Tsunami(const std::string &name, ScsiController *scsi,
EtherDev *ethernet,
SimConsole *, IntrControl *intctrl, int intrFreq);