fullsys now builds and runs for about one cycle

SConscript:
    easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    mem needed for both fullsys and syscall
dev/baddev.cc:
    fix for new mem system
dev/io_device.cc:
    fix typo
dev/io_device.hh:
    PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
    fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
    rather than the platform have a pointer to pciconfig, go the other
    way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    fixes for newmem

--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105

1 files changed, 6 insertions, 14 deletions

diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 645b64d14..b15f6fefb 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -71,16 +71,15 @@ TsunamiCChip::TsunamiCChip(Params *p)
 Tick
 TsunamiCChip::read(Packet &pkt)
 {
-    DPRINTF(Tsunami, "read  va=%#x size=%d\n", req->vaddr, req->size);
+    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt.addr, pkt.size);
 
     assert(pkt.result == Unknown);
     assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
 
     pkt.time = curTick + pioDelay;
-    Addr regnum = (req->paddr - pioAddr) >> 6;
-    Addr daddr = (req->paddr - pioAddr);
+    Addr regnum = (pkt.addr - pioAddr) >> 6;
+    Addr daddr = (pkt.addr - pioAddr);
 
-    uint32_t *data32;
     uint64_t *data64;
 
     switch (pkt.size) {
@@ -113,7 +112,7 @@ TsunamiCChip::read(Packet &pkt)
                    break;
               case TSDEV_CC_MISC:
                   *data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF |
-                                     (pkt.req->cpuId & 0x3);
+                                     (pkt.req->getCpuNum() & 0x3);
                   break;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
@@ -181,7 +180,7 @@ TsunamiCChip::read(Packet &pkt)
         panic("invalid access size(?) for tsunami register!\n");
     }
     DPRINTFN("Tsunami CChip: read  regnum=%#x size=%d data=%lld\n", regnum,
-            req->size, *data);
+            pkt.size, *data64);
 
     pkt.result = Success;
     return pioDelay;
@@ -201,7 +200,7 @@ TsunamiCChip::write(Packet &pkt)
     uint64_t val = *(uint64_t *)pkt.data;
     assert(pkt.size == sizeof(uint64_t));
 
-    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", req->addr, val);
+    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val);
 
     bool supportedWrite = false;
 
@@ -289,7 +288,6 @@ TsunamiCChip::write(Packet &pkt)
             case TSDEV_CC_AAR2:
             case TSDEV_CC_AAR3:
                 panic("TSDEV_CC_AARx write not implemeted\n");
-                return NoFault;
             case TSDEV_CC_DIM0:
             case TSDEV_CC_DIM1:
             case TSDEV_CC_DIM2:
@@ -508,12 +506,6 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
         DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
 }
 
-Tick
-TsunamiCChip::cacheAccess(MemReqPtr &req)
-{
-    return curTick + pioLatency;
-}
-
 
 void
 TsunamiCChip::serialize(std::ostream &os)