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author | Ali Saidi <saidi@eecs.umich.edu> | 2005-02-03 23:50:57 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2005-02-03 23:50:57 -0500 |
commit | 7e559f6c50e38272a6f2ab46ea49394413597634 (patch) | |
tree | b516039f93f0fe09b003400123d2f0b7d63c142e /dev/tsunami_cchip.cc | |
parent | 52403a5ddf1e02f53d0624254f41e27e3914df29 (diff) | |
download | gem5-7e559f6c50e38272a6f2ab46ea49394413597634.tar.xz |
Add Monet configuration, update p4 parameters, couple of typo fixes
dev/tsunami_cchip.cc:
add a fake register to tsunami that we can do 32bit reads to.
Warn on access.
--HG--
extra : convert_revision : d87860f3b527528151c23431556039bca6e12945
Diffstat (limited to 'dev/tsunami_cchip.cc')
-rw-r--r-- | dev/tsunami_cchip.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 823d1f118..6bf4d8b57 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -173,6 +173,13 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) break; case sizeof(uint32_t): + if (regnum == TSDEV_CC_DRIR) { + warn("accessing DRIR with 32 bit read, " + "hopefully your just reading this for timing"); + *(uint64_t*)data = drir; + } else + panic("invalid access size(?) for tsunami register!\n"); + return No_Fault; case sizeof(uint16_t): case sizeof(uint8_t): default: |