diff options
author | Nathan Binkert <binkertn@umich.edu> | 2004-07-12 22:58:22 -0400 |
---|---|---|
committer | Nathan Binkert <binkertn@umich.edu> | 2004-07-12 22:58:22 -0400 |
commit | 13f8dc981fc898e6e200689d305b39f0718f8c83 (patch) | |
tree | e75ced9115aef60e6c173e08633e19ba92b62569 /dev/tsunami_cchip.cc | |
parent | c2e5caf3606b85b6f45cde53b8021692ef01710e (diff) | |
download | gem5-13f8dc981fc898e6e200689d305b39f0718f8c83.tar.xz |
make the cache access latency a parameter that is based on bus
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
Diffstat (limited to 'dev/tsunami_cchip.cc')
-rw-r--r-- | dev/tsunami_cchip.cc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 0fbfcb56f..870924a2f 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -49,7 +49,8 @@ using namespace std; TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, - MemoryController *mmu, HierParams *hier, Bus* bus) + MemoryController *mmu, HierParams *hier, Bus* bus, + Tick pio_latency) : PioDevice(name), addr(a), tsunami(t) { mmu->add_child(this, Range<Addr>(addr, addr + size)); @@ -66,6 +67,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, pioInterface = newPioInterface(name, hier, bus, this, &TsunamiCChip::cacheAccess); pioInterface->addAddrRange(addr, addr + size - 1); + pioLatency = pio_latency * bus->clockRatio; } drir = 0; @@ -383,7 +385,7 @@ TsunamiCChip::clearDRIR(uint32_t interrupt) Tick TsunamiCChip::cacheAccess(MemReqPtr &req) { - return curTick + 1000; + return curTick + pioLatency; } @@ -417,6 +419,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) SimObjectParam<MemoryController *> mmu; Param<Addr> addr; SimObjectParam<Bus*> io_bus; + Param<Tick> pio_latency; SimObjectParam<HierParams *> hier; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) @@ -427,13 +430,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) INIT_PARAM(mmu, "Memory Controller"), INIT_PARAM(addr, "Device Address"), INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) CREATE_SIM_OBJECT(TsunamiCChip) { - return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus); + return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, + io_bus, pio_latency); } REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) |