diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-04-11 13:43:15 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-04-11 13:43:15 -0400 |
| commit | 194fb50fbd3f00577ce129762c9a8f13c721e4ad (patch) | |
| tree | fa464892deda45dae86ff3c847cc7ae9aea0db22 /dev/tsunami_cchip.cc | |
| parent | da7990ab337699ae788809ddaea5ba5c363e0015 (diff) | |
| parent | f6fc18f03d639098b1421fa3412329773b0a6ab1 (diff) | |
| download | gem5-194fb50fbd3f00577ce129762c9a8f13c721e4ad.tar.xz | |
Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision : ef75b46b9c1c267c84e6bb2b2234d46c4edcda16
Diffstat (limited to 'dev/tsunami_cchip.cc')
| -rw-r--r-- | dev/tsunami_cchip.cc | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 645b64d14..b15f6fefb 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -71,16 +71,15 @@ TsunamiCChip::TsunamiCChip(Params *p) Tick TsunamiCChip::read(Packet &pkt) { - DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); + DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size); assert(pkt.result == Unknown); assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize); pkt.time = curTick + pioDelay; - Addr regnum = (req->paddr - pioAddr) >> 6; - Addr daddr = (req->paddr - pioAddr); + Addr regnum = (pkt.addr - pioAddr) >> 6; + Addr daddr = (pkt.addr - pioAddr); - uint32_t *data32; uint64_t *data64; switch (pkt.size) { @@ -113,7 +112,7 @@ TsunamiCChip::read(Packet &pkt) break; case TSDEV_CC_MISC: *data64 = (ipint << 8) & 0xF | (itint << 4) & 0xF | - (pkt.req->cpuId & 0x3); + (pkt.req->getCpuNum() & 0x3); break; case TSDEV_CC_AAR0: case TSDEV_CC_AAR1: @@ -181,7 +180,7 @@ TsunamiCChip::read(Packet &pkt) panic("invalid access size(?) for tsunami register!\n"); } DPRINTFN("Tsunami CChip: read regnum=%#x size=%d data=%lld\n", regnum, - req->size, *data); + pkt.size, *data64); pkt.result = Success; return pioDelay; @@ -201,7 +200,7 @@ TsunamiCChip::write(Packet &pkt) uint64_t val = *(uint64_t *)pkt.data; assert(pkt.size == sizeof(uint64_t)); - DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", req->addr, val); + DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt.addr, val); bool supportedWrite = false; @@ -289,7 +288,6 @@ TsunamiCChip::write(Packet &pkt) case TSDEV_CC_AAR2: case TSDEV_CC_AAR3: panic("TSDEV_CC_AARx write not implemeted\n"); - return NoFault; case TSDEV_CC_DIM0: case TSDEV_CC_DIM1: case TSDEV_CC_DIM2: @@ -508,12 +506,6 @@ TsunamiCChip::clearDRIR(uint32_t interrupt) DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); } -Tick -TsunamiCChip::cacheAccess(MemReqPtr &req) -{ - return curTick + pioLatency; -} - void TsunamiCChip::serialize(std::ostream &os) |