Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.

SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d

1 files changed, 34 insertions, 34 deletions

diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 2287a2a3d..4cda9ec36 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -76,7 +76,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
     tsunami->cchip = this;
 }
 
-Fault
+Fault *
 TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "read  va=%#x size=%d\n", req->vaddr, req->size);
@@ -92,81 +92,81 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
           if (daddr & TSDEV_CC_BDIMS)
           {
               *(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
-              return No_Fault;
+              return NoFault;
           }
 
           if (daddr & TSDEV_CC_BDIRS)
           {
               *(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
-              return No_Fault;
+              return NoFault;
           }
 
           switch(regnum) {
               case TSDEV_CC_CSR:
                   *(uint64_t*)data = 0x0;
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_MTR:
                   panic("TSDEV_CC_MTR not implemeted\n");
-                   return No_Fault;
+                   return NoFault;
               case TSDEV_CC_MISC:
                   *(uint64_t*)data = (ipint << 8) & 0xF |
                                      (itint << 4) & 0xF |
                                      (xc->cpu_id & 0x3);
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
               case TSDEV_CC_AAR2:
               case TSDEV_CC_AAR3:
                   *(uint64_t*)data = 0;
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIM0:
                   *(uint64_t*)data = dim[0];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIM1:
                   *(uint64_t*)data = dim[1];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIM2:
                   *(uint64_t*)data = dim[2];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIM3:
                   *(uint64_t*)data = dim[3];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIR0:
                   *(uint64_t*)data = dir[0];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIR1:
                   *(uint64_t*)data = dir[1];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIR2:
                   *(uint64_t*)data = dir[2];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIR3:
                   *(uint64_t*)data = dir[3];
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DRIR:
                   *(uint64_t*)data = drir;
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_PRBEN:
                   panic("TSDEV_CC_PRBEN not implemented\n");
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_IIC0:
               case TSDEV_CC_IIC1:
               case TSDEV_CC_IIC2:
               case TSDEV_CC_IIC3:
                   panic("TSDEV_CC_IICx not implemented\n");
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_MPR0:
               case TSDEV_CC_MPR1:
               case TSDEV_CC_MPR2:
               case TSDEV_CC_MPR3:
                   panic("TSDEV_CC_MPRx not implemented\n");
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_IPIR:
                   *(uint64_t*)data = ipint;
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_ITIR:
                   *(uint64_t*)data = itint;
-                  return No_Fault;
+                  return NoFault;
               default:
                   panic("default in cchip read reached, accessing 0x%x\n");
            } // uint64_t
@@ -179,7 +179,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
               *(uint32_t*)data = drir;
           } else
               panic("invalid access size(?) for tsunami register!\n");
-          return No_Fault;
+          return NoFault;
       case sizeof(uint16_t):
       case sizeof(uint8_t):
       default:
@@ -187,10 +187,10 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
     }
     DPRINTFN("Tsunami CChip ERROR: read  regnum=%#x size=%d\n", regnum, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
-Fault
+Fault *
 TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 {
     DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
@@ -243,16 +243,16 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 
                   }
               }
-              return No_Fault;
+              return NoFault;
           }
 
           switch(regnum) {
               case TSDEV_CC_CSR:
                   panic("TSDEV_CC_CSR write\n");
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_MTR:
                   panic("TSDEV_CC_MTR write not implemented\n");
-                   return No_Fault;
+                   return NoFault;
               case TSDEV_CC_MISC:
                 uint64_t ipreq;
                 ipreq = (*(uint64_t*)data >> 12) & 0xF;
@@ -285,13 +285,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
                 if(!supportedWrite)
                     panic("TSDEV_CC_MISC write not implemented\n");
 
-                return No_Fault;
+                return NoFault;
               case TSDEV_CC_AAR0:
               case TSDEV_CC_AAR1:
               case TSDEV_CC_AAR2:
               case TSDEV_CC_AAR3:
                   panic("TSDEV_CC_AARx write not implemeted\n");
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIM0:
               case TSDEV_CC_DIM1:
               case TSDEV_CC_DIM2:
@@ -341,7 +341,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 
                       }
                   }
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_DIR0:
               case TSDEV_CC_DIR1:
               case TSDEV_CC_DIR2:
@@ -363,13 +363,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
                   panic("TSDEV_CC_MPRx write not implemented\n");
               case TSDEV_CC_IPIR:
                   clearIPI(*(uint64_t*)data);
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_ITIR:
                   clearITI(*(uint64_t*)data);
-                  return No_Fault;
+                  return NoFault;
               case TSDEV_CC_IPIQ:
                   reqIPI(*(uint64_t*)data);
-                  return No_Fault;
+                  return NoFault;
               default:
                   panic("default in cchip read reached, accessing 0x%x\n");
           }
@@ -384,7 +384,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 
     DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
 void