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authorAli Saidi <saidi@eecs.umich.edu>2004-02-05 13:05:20 -0500
committerAli Saidi <saidi@eecs.umich.edu>2004-02-05 13:05:20 -0500
commit7a6a435983e368fba244ec0d6d18e2f7fcf73ee3 (patch)
tree989754f0114ab1a4cf85d55af4ff872b384c46e5 /dev/tsunami_cchip.hh
parent69e1e10f5d940ee06d2c38f3a1b21c9992587f13 (diff)
downloadgem5-7a6a435983e368fba244ec0d6d18e2f7fcf73ee3.tar.xz
added some comments
--HG-- extra : convert_revision : b33c94984f8d9ac2baf8d7b45fa79460846b1755
Diffstat (limited to 'dev/tsunami_cchip.hh')
-rw-r--r--dev/tsunami_cchip.hh22
1 files changed, 21 insertions, 1 deletions
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index a79e60cfc..16d795afb 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -27,7 +27,7 @@
*/
/* @file
- * Turbolaser system bus node (processor, memory, or IO)
+ * Emulation of the Tsunami CChip CSRs
*/
#ifndef __TSUNAMI_CCHIP_HH__
@@ -44,10 +44,30 @@ class TsunamiCChip : public MmapDevice
public:
protected:
+ /**
+ * pointer to the tsunami object.
+ * This is our access to all the other tsunami
+ * devices.
+ */
Tsunami *tsunami;
+
+ /**
+ * The dims are device interrupt mask registers.
+ * One exists for each CPU, the DRIR X DIM = DIR
+ */
uint64_t dim[Tsunami::Max_CPUs];
+
+ /**
+ * The dirs are device interrupt registers.
+ * One exists for each CPU, the DRIR X DIM = DIR
+ */
uint64_t dir[Tsunami::Max_CPUs];
bool dirInterrupting[Tsunami::Max_CPUs];
+
+ /**
+ * This register contains bits for each PCI interrupt
+ * that can occur.
+ */
uint64_t drir;
public: