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author | Ali Saidi <saidi@eecs.umich.edu> | 2004-01-21 20:14:10 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-01-21 20:14:10 -0500 |
commit | 0e805e1ff35a5c70f8aff785db709c1f3b8d0c28 (patch) | |
tree | 477c44468c2133786843d587e5b16a583bd49897 /dev/tsunami_dma.cc | |
parent | cb51c1503c6b860e1f848e227d07a773f94f23b6 (diff) | |
download | gem5-0e805e1ff35a5c70f8aff785db709c1f3b8d0c28.tar.xz |
one step closer to booting
dev/alpha_access.h:
removed my attempted hack to get console compling in linux
dev/tsunami.cc:
dev/tsunami.hh:
added pchip pointer to tsunami
dev/tsunami_cchip.cc:
made printing better
dev/tsunami_cchip.hh:
commented out back pointer for now, since the parser has issues with it
dev/tsunamireg.h:
added pchip registers
--HG--
extra : convert_revision : b4fceb7d08e757d9aaf37df8eb1bcd5ae29ce0da
Diffstat (limited to 'dev/tsunami_dma.cc')
-rw-r--r-- | dev/tsunami_dma.cc | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/dev/tsunami_dma.cc b/dev/tsunami_dma.cc new file mode 100644 index 000000000..d52cf2b8f --- /dev/null +++ b/dev/tsunami_dma.cc @@ -0,0 +1,93 @@ +/* $Id$ */ + +/* @file + * Tsunami DMA fake + */ + +#include <deque> +#include <string> +#include <vector> + +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "dev/console.hh" +#include "dev/etherdev.hh" +#include "dev/scsi_ctrl.hh" +#include "dev/tlaser_clock.hh" +#include "dev/tsunami_dma.hh" +#include "dev/tsunamireg.h" +#include "dev/tsunami.hh" +#include "mem/functional_mem/memory_control.hh" +#include "sim/builder.hh" +#include "sim/system.hh" + +using namespace std; + +TsunamiDMA::TsunamiDMA(const string &name, /*Tsunami *t,*/ + Addr addr, Addr mask, MemoryController *mmu) + : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */ +{ + +} + +Fault +TsunamiDMA::read(MemReqPtr req, uint8_t *data) +{ + DPRINTF(Tsunami, "dma read va=%#x size=%d IOPorrt=%#x\n", + req->vaddr, req->size, req->vaddr & 0xfff); + + // Addr daddr = (req->paddr & addr_mask) >> 6; +// ExecContext *xc = req->xc; +// int cpuid = xc->cpu_id; + *(uint64_t*)data = 0x00; + + return No_Fault; +} + +Fault +TsunamiDMA::write(MemReqPtr req, const uint8_t *data) +{ + DPRINTF(Tsunami, "dma write - va=%#x size=%d IOPort=%#x\n", + req->vaddr, req->size, req->vaddr & 0xfff); + + //Addr daddr = (req->paddr & addr_mask) >> 6; + + return No_Fault; +} + +void +TsunamiDMA::serialize(std::ostream &os) +{ + // code should be written +} + +void +TsunamiDMA::unserialize(Checkpoint *cp, const std::string §ion) +{ + //code should be written +} + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiDMA) + + // SimObjectParam<Tsunami *> tsunami; + SimObjectParam<MemoryController *> mmu; + Param<Addr> addr; + Param<Addr> mask; + +END_DECLARE_SIM_OBJECT_PARAMS(TsunamiDMA) + +BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiDMA) + +// INIT_PARAM(tsunami, "Tsunami"), + INIT_PARAM(mmu, "Memory Controller"), + INIT_PARAM(addr, "Device Address"), + INIT_PARAM(mask, "Address Mask") + +END_INIT_SIM_OBJECT_PARAMS(TsunamiDMA) + +CREATE_SIM_OBJECT(TsunamiDMA) +{ + return new TsunamiDMA(getInstanceName(), /*tsunami,*/ addr, mask, mmu); +} + +REGISTER_SIM_OBJECT("TsunamiDMA", TsunamiDMA) |