Various changes to I/O, addition of PciFake device to improve FreeBSD compatibility.

SConscript:
    Include pcifake.cc, fix spacing.
dev/ide_ctrl.cc:
    Consolidate switch-case blocks.
dev/ide_disk.cc:
    Add comments.
dev/pciconfigall.cc:
    Adjust spacing.
dev/pcidev.cc:
    Adjust spacing, rearrange code.
dev/tsunami_io.cc:
    Rearrange code.
dev/uart8250.cc:
    Switch uart interrupt interval back to original value.
python/m5/objects/Pci.py:
    Add PciFake class to be used as a PCI-ISA bridge device.

--HG--
extra : convert_revision : 8aea94318510079a310377f297aa161ba5f7864c

1 files changed, 3 insertions, 4 deletions

diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 6a704f7ac..82fe40e0a 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -75,7 +75,6 @@ TsunamiIO::RTCEvent::process()
         tm.tm_sec = (tm.tm_sec + 1) % 60;
 
     intr_count = (intr_count + 1) % 1024;
-
 }
 
 const char *
@@ -316,15 +315,15 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
                 return No_Fault;
               case RTC_CNTRL_REGD:
                 panic("RTC Control Register D not implemented");
-              case RTC_SEC:
-                *(uint8_t *)data = tm.tm_sec;
-                return No_Fault;
               case RTC_SEC_ALRM:
               case RTC_MIN_ALRM:
               case RTC_HR_ALRM:
                 // RTC alarm functionality is not currently implemented
                 *(uint8_t *)data = 0x00;
                 return No_Fault;
+              case RTC_SEC:
+                *(uint8_t *)data = tm.tm_sec;
+                return No_Fault;
               case RTC_MIN:
                 *(uint8_t *)data = tm.tm_min;
                 return No_Fault;