Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.

SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d

1 files changed, 35 insertions, 35 deletions

diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 724a5bfb9..0d0d27570 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -444,7 +444,7 @@ TsunamiIO::frequency() const
     return Clock::Frequency / clockInterval;
 }
 
-Fault
+Fault *
 TsunamiIO::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n",
@@ -459,38 +459,38 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
           // PIC1 mask read
           case TSDEV_PIC1_MASK:
             *(uint8_t*)data = ~mask1;
-            return No_Fault;
+            return NoFault;
           case TSDEV_PIC2_MASK:
             *(uint8_t*)data = ~mask2;
-            return No_Fault;
+            return NoFault;
           case TSDEV_PIC1_ISR:
               // !!! If this is modified 64bit case needs to be too
               // Pal code has to do a 64 bit physical read because there is
               // no load physical byte instruction
               *(uint8_t*)data = picr;
-              return No_Fault;
+              return NoFault;
           case TSDEV_PIC2_ISR:
               // PIC2 not implemnted... just return 0
               *(uint8_t*)data = 0x00;
-              return No_Fault;
+              return NoFault;
           case TSDEV_TMR0_DATA:
             pitimer.counter0.read(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_TMR1_DATA:
             pitimer.counter1.read(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_TMR2_DATA:
             pitimer.counter2.read(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_RTC_DATA:
             rtc.readData(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_CTRL_PORTB:
             if (pitimer.counter2.outputHigh())
                 *data = PORTB_SPKR_HIGH;
             else
                 *data = 0x00;
-            return No_Fault;
+            return NoFault;
           default:
             panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
         }
@@ -506,7 +506,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
               // Pal code has to do a 64 bit physical read because there is
               // no load physical byte instruction
               *(uint64_t*)data = (uint64_t)picr;
-              return No_Fault;
+              return NoFault;
           default:
               panic("I/O Read - invalid size - va %#x size %d\n",
                     req->vaddr, req->size);
@@ -518,10 +518,10 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
     }
     panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
-Fault
+Fault *
 TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
 {
 
@@ -550,63 +550,63 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
                 tsunami->cchip->clearDRIR(55);
                 DPRINTF(Tsunami, "clearing pic interrupt\n");
             }
-            return No_Fault;
+            return NoFault;
           case TSDEV_PIC2_MASK:
             mask2 = *(uint8_t*)data;
             //PIC2 Not implemented to interrupt
-            return No_Fault;
+            return NoFault;
           case TSDEV_PIC1_ACK:
             // clear the interrupt on the PIC
             picr &= ~(1 << (*(uint8_t*)data & 0xF));
             if (!(picr & mask1))
                 tsunami->cchip->clearDRIR(55);
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA1_CMND:
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA2_CMND:
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA1_MMASK:
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA2_MMASK:
-            return No_Fault;
+            return NoFault;
           case TSDEV_PIC2_ACK:
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA1_RESET:
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA2_RESET:
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA1_MODE:
             mode1 = *(uint8_t*)data;
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA2_MODE:
             mode2 = *(uint8_t*)data;
-            return No_Fault;
+            return NoFault;
           case TSDEV_DMA1_MASK:
           case TSDEV_DMA2_MASK:
-            return No_Fault;
+            return NoFault;
           case TSDEV_TMR0_DATA:
             pitimer.counter0.write(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_TMR1_DATA:
             pitimer.counter1.write(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_TMR2_DATA:
             pitimer.counter2.write(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_TMR_CTRL:
             pitimer.writeControl(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_RTC_ADDR:
             rtc.writeAddr(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_KBD:
-            return No_Fault;
+            return NoFault;
           case TSDEV_RTC_DATA:
             rtc.writeData(data);
-            return No_Fault;
+            return NoFault;
           case TSDEV_CTRL_PORTB:
             // System Control Port B not implemented
-            return No_Fault;
+            return NoFault;
           default:
             panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
         }
@@ -619,7 +619,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
     }
 
 
-    return No_Fault;
+    return NoFault;
 }
 
 void