Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

1 files changed, 25 insertions, 44 deletions

diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index ebf3492ac..ed526bdde 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -447,65 +447,51 @@ TsunamiIO::read(Packet &pkt)
     DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n", pkt.addr,
             pkt.size, daddr);
 
-
-    uint8_t *data8;
-    uint64_t *data64;
+    pkt.allocate();
 
     if (pkt.size == sizeof(uint8_t)) {
-
-        if (!pkt.data) {
-            data8 = new uint8_t;
-            pkt.data = data8;
-        } else
-            data8 = pkt.data;
         switch(daddr) {
           // PIC1 mask read
           case TSDEV_PIC1_MASK:
-            *data8 = ~mask1;
+            pkt.set(~mask1);
             break;
           case TSDEV_PIC2_MASK:
-            *data8 = ~mask2;
+            pkt.set(~mask2);
             break;
           case TSDEV_PIC1_ISR:
               // !!! If this is modified 64bit case needs to be too
               // Pal code has to do a 64 bit physical read because there is
               // no load physical byte instruction
-              *data8 = picr;
+              pkt.set(picr);
               break;
           case TSDEV_PIC2_ISR:
               // PIC2 not implemnted... just return 0
-              *data8 = 0x00;
+              pkt.set(0x00);
               break;
           case TSDEV_TMR0_DATA:
-            pitimer.counter0.read(data8);
+            pitimer.counter0.read(pkt.getPtr<uint8_t>());
             break;
           case TSDEV_TMR1_DATA:
-            pitimer.counter1.read(data8);
+            pitimer.counter1.read(pkt.getPtr<uint8_t>());
             break;
           case TSDEV_TMR2_DATA:
-            pitimer.counter2.read(data8);
+            pitimer.counter2.read(pkt.getPtr<uint8_t>());
             break;
           case TSDEV_RTC_DATA:
-            rtc.readData(data8);
+            rtc.readData(pkt.getPtr<uint8_t>());
             break;
           case TSDEV_CTRL_PORTB:
             if (pitimer.counter2.outputHigh())
-                *data8 = PORTB_SPKR_HIGH;
+                pkt.set(PORTB_SPKR_HIGH);
             else
-                *data8 = 0x00;
+                pkt.set(0x00);
             break;
           default:
             panic("I/O Read - va%#x size %d\n", pkt.addr, pkt.size);
         }
     } else if (pkt.size == sizeof(uint64_t)) {
-        if (!pkt.data) {
-            data64 = new uint64_t;
-            pkt.data = (uint8_t*)data64;
-        } else
-            data64 = (uint64_t*)pkt.data;
-
         if (daddr == TSDEV_PIC1_ISR)
-            *data64 = picr;
+            pkt.set<uint64_t>(picr);
         else
            panic("I/O Read - invalid addr - va %#x size %d\n",
                    pkt.addr, pkt.size);
@@ -524,20 +510,15 @@ TsunamiIO::write(Packet &pkt)
     assert(pkt.result == Unknown);
     assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
     Addr daddr = pkt.addr - pioAddr;
-    uint8_t val = *pkt.data;
-
-#if TRACING_ON
-    uint64_t dt64 = val;
-#endif
 
     DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
-            pkt.addr, pkt.size, pkt.addr & 0xfff, dt64);
+            pkt.addr, pkt.size, pkt.addr & 0xfff, (uint32_t)pkt.get<uint8_t>());
 
     assert(pkt.size == sizeof(uint8_t));
 
     switch(daddr) {
       case TSDEV_PIC1_MASK:
-        mask1 = ~(val);
+        mask1 = ~(pkt.get<uint8_t>());
         if ((picr & mask1) && !picInterrupting) {
             picInterrupting = true;
             tsunami->cchip->postDRIR(55);
@@ -550,38 +531,38 @@ TsunamiIO::write(Packet &pkt)
         }
         break;
       case TSDEV_PIC2_MASK:
-        mask2 = val;
+        mask2 = pkt.get<uint8_t>();
         //PIC2 Not implemented to interrupt
         break;
       case TSDEV_PIC1_ACK:
         // clear the interrupt on the PIC
-        picr &= ~(1 << (val & 0xF));
+        picr &= ~(1 << (pkt.get<uint8_t>() & 0xF));
         if (!(picr & mask1))
             tsunami->cchip->clearDRIR(55);
         break;
       case TSDEV_DMA1_MODE:
-        mode1 = val;
+        mode1 = pkt.get<uint8_t>();
         break;
       case TSDEV_DMA2_MODE:
-        mode2 = val;
+        mode2 = pkt.get<uint8_t>();
         break;
       case TSDEV_TMR0_DATA:
-        pitimer.counter0.write(val);
+        pitimer.counter0.write(pkt.get<uint8_t>());
         break;
       case TSDEV_TMR1_DATA:
-        pitimer.counter1.write(val);
+        pitimer.counter1.write(pkt.get<uint8_t>());
         break;
       case TSDEV_TMR2_DATA:
-        pitimer.counter2.write(val);
+        pitimer.counter2.write(pkt.get<uint8_t>());
         break;
       case TSDEV_TMR_CTRL:
-        pitimer.writeControl(val);
+        pitimer.writeControl(pkt.get<uint8_t>());
         break;
       case TSDEV_RTC_ADDR:
-        rtc.writeAddr(val);
+        rtc.writeAddr(pkt.get<uint8_t>());
         break;
       case TSDEV_RTC_DATA:
-        rtc.writeData(val);
+        rtc.writeData(pkt.get<uint8_t>());
         break;
       case TSDEV_KBD:
       case TSDEV_DMA1_CMND:
@@ -596,7 +577,7 @@ TsunamiIO::write(Packet &pkt)
       case TSDEV_CTRL_PORTB:
         break;
       default:
-        panic("I/O Write - va%#x size %d data %#x\n", pkt.addr, pkt.size, val);
+        panic("I/O Write - va%#x size %d data %#x\n", pkt.addr, pkt.size, pkt.get<uint8_t>());
     }
 
     pkt.result = Success;