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authorAli Saidi <saidi@eecs.umich.edu>2006-04-11 13:42:47 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-04-11 13:42:47 -0400
commitf6fc18f03d639098b1421fa3412329773b0a6ab1 (patch)
tree423a91facc95cb08962c2d66906a3a1b2dbeb49b /dev/tsunami_io.hh
parent93b271117f8fc93b844b08934ee8fcfa5224053d (diff)
downloadgem5-f6fc18f03d639098b1421fa3412329773b0a6ab1.tar.xz
fullsys now builds and runs for about one cycle
SConscript: easier to fix than temporarily remove cpu/simple/cpu.cc: cpu/simple/cpu.hh: mem needed for both fullsys and syscall dev/baddev.cc: fix for new mem system dev/io_device.cc: fix typo dev/io_device.hh: PioDevice needs to be a memobject dev/isa_fake.cc: dev/pciconfigall.cc: dev/pciconfigall.hh: fix for new mem systems dev/platform.cc: dev/platform.hh: dev/tsunami.cc: dev/tsunami.hh: rather than the platform have a pointer to pciconfig, go the other way so all devices are the same and can have a platform pointer dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart8250.cc: python/m5/objects/AlphaConsole.py: python/m5/objects/BadDevice.py: python/m5/objects/BaseCPU.py: python/m5/objects/Device.py: python/m5/objects/Pci.py: python/m5/objects/PhysicalMemory.py: python/m5/objects/System.py: python/m5/objects/Tsunami.py: python/m5/objects/Uart.py: fixes for newmem --HG-- extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
Diffstat (limited to 'dev/tsunami_io.hh')
-rw-r--r--dev/tsunami_io.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh
index defb850ce..c37f3aa16 100644
--- a/dev/tsunami_io.hh
+++ b/dev/tsunami_io.hh
@@ -42,7 +42,7 @@
* Tsunami I/O device is a catch all for all the south bridge stuff we care
* to implement.
*/
-class TsunamiIO : public PioDevice
+class TsunamiIO : public BasicPioDevice
{
private:
struct tm tm;
@@ -318,8 +318,8 @@ class TsunamiIO : public PioDevice
*/
TsunamiIO(Params *p);
- virtual Fault read(Packet &pkt);
- virtual Fault write(Packet &pkt);
+ virtual Tick read(Packet &pkt);
+ virtual Tick write(Packet &pkt);
/**
* Post an PIC interrupt to the CPU via the CChip