Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.

SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d

1 files changed, 35 insertions, 35 deletions

diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index e61137170..a4c04a79f 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -76,7 +76,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
     tsunami->pchip = this;
 }
 
-Fault
+Fault *
 TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
@@ -90,60 +90,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
           switch(daddr) {
               case TSDEV_PC_WSBA0:
                     *(uint64_t*)data = wsba[0];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA1:
                     *(uint64_t*)data = wsba[1];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA2:
                     *(uint64_t*)data = wsba[2];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA3:
                     *(uint64_t*)data = wsba[3];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM0:
                     *(uint64_t*)data = wsm[0];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM1:
                     *(uint64_t*)data = wsm[1];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM2:
                     *(uint64_t*)data = wsm[2];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM3:
                     *(uint64_t*)data = wsm[3];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA0:
                     *(uint64_t*)data = tba[0];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA1:
                     *(uint64_t*)data = tba[1];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA2:
                     *(uint64_t*)data = tba[2];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA3:
                     *(uint64_t*)data = tba[3];
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PCTL:
                     *(uint64_t*)data = pctl;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PLAT:
                     panic("PC_PLAT not implemented\n");
               case TSDEV_PC_RES:
                     panic("PC_RES not implemented\n");
               case TSDEV_PC_PERROR:
                     *(uint64_t*)data = 0x00;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PERRMASK:
                     *(uint64_t*)data = 0x00;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PERRSET:
                     panic("PC_PERRSET not implemented\n");
               case TSDEV_PC_TLBIV:
                     panic("PC_TLBIV not implemented\n");
               case TSDEV_PC_TLBIA:
                     *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PMONCTL:
                     panic("PC_PMONCTL not implemented\n");
               case TSDEV_PC_PMONCNT:
@@ -162,10 +162,10 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
     }
     DPRINTFN("Tsunami PChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
-Fault
+Fault *
 TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
 {
     DPRINTF(Tsunami, "write - va=%#x size=%d \n",
@@ -179,49 +179,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
           switch(daddr) {
               case TSDEV_PC_WSBA0:
                     wsba[0] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA1:
                     wsba[1] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA2:
                     wsba[2] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSBA3:
                     wsba[3] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM0:
                     wsm[0] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM1:
                     wsm[1] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM2:
                     wsm[2] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_WSM3:
                     wsm[3] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA0:
                     tba[0] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA1:
                     tba[1] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA2:
                     tba[2] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_TBA3:
                     tba[3] = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PCTL:
                     pctl = *(uint64_t*)data;
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PLAT:
                     panic("PC_PLAT not implemented\n");
               case TSDEV_PC_RES:
                     panic("PC_RES not implemented\n");
               case TSDEV_PC_PERROR:
-                    return No_Fault;
+                    return NoFault;
               case TSDEV_PC_PERRMASK:
                     panic("PC_PERRMASK not implemented\n");
               case TSDEV_PC_PERRSET:
@@ -229,7 +229,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
               case TSDEV_PC_TLBIV:
                     panic("PC_TLBIV not implemented\n");
               case TSDEV_PC_TLBIA:
-                    return No_Fault; // value ignored, supposted to invalidate SG TLB
+                    return NoFault; // value ignored, supposted to invalidate SG TLB
               case TSDEV_PC_PMONCTL:
                     panic("PC_PMONCTL not implemented\n");
               case TSDEV_PC_PMONCNT:
@@ -249,7 +249,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
 
     DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
 
-    return No_Fault;
+    return NoFault;
 }
 
 #define DMA_ADDR_MASK ULL(0x3ffffffff)