Linux boots... various fixes to make console work correctly

dev/console.cc:
    commented out code that checks if an interrupt is happening before issuing one
    because they can get lost when linux boots
dev/console.hh:
    added a setPlatform function to set the platform to interrupt
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
    Added virtual functions to post console interrupts
dev/tsunami_io.cc:
    allowed a 64bit read of the PIC since we can't do a physical byte read
dev/tsunami_uart.cc:
    moved TsunamiUart to PioDevice
    various little fixes to make linux work
dev/tsunami_uart.hh:
    Made Tsunami_Uart a PIO device
dev/tsunamireg.h:
    added some UART defines and used the ULL macros
kern/linux/linux_system.cc:
    commented out waiting for gdb

--HG--
extra : convert_revision : 8cfd0700f3812ab349a6d7f132f85f4f421c5c5e

1 files changed, 9 insertions, 4 deletions

diff --git a/dev/tsunami_uart.hh b/dev/tsunami_uart.hh
index f0a9b644b..d57b255ae 100644
--- a/dev/tsunami_uart.hh
+++ b/dev/tsunami_uart.hh
@@ -33,14 +33,16 @@
 #ifndef __TSUNAMI_UART_HH__
 #define __TSUNAMI_UART_HH__
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "dev/tsunamireg.h"
+#include "base/range.hh"
+#include "dev/io_device.hh"
 
 class SimConsole;
 
 /*
  * Tsunami UART
  */
-class TsunamiUart : public FunctionalMemory
+class TsunamiUart : public PioDevice
 {
   private:
     Addr addr;
@@ -54,8 +56,8 @@ class TsunamiUart : public FunctionalMemory
     uint8_t IER;
 
   public:
-    TsunamiUart(const std::string &name, SimConsole *c, Addr a,
-                MemoryController *mmu);
+    TsunamiUart(const string &name, SimConsole *c, MemoryController *mmu,
+            Addr a, HierParams *hier, Bus *bus);
 
     Fault read(MemReqPtr &req, uint8_t *data);
     Fault write(MemReqPtr &req, const uint8_t *data);
@@ -63,6 +65,9 @@ class TsunamiUart : public FunctionalMemory
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+  public:
+    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __TSUNAMI_UART_HH__