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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-12-06 12:06:16 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-12-06 12:06:16 -0500 |
| commit | 34260bbf0da0aa735ddcc701441cac71fee1e5b0 (patch) | |
| tree | 4d26b0c597523b580bb5a5f47d44173ef7a7b079 /dev/tsunamireg.h | |
| parent | 46b5f8dfc18248a02ffc390fc70b929a12649c9d (diff) | |
| download | gem5-34260bbf0da0aa735ddcc701441cac71fee1e5b0.tar.xz | |
Add support for Tsunami with 64 processors
base/socket.cc:
Make panic print a more worthwhile message
dev/tsunami.hh:
Change max number of tsunami cpus to be 64
dev/tsunamireg.h:
Add new registers and register blocks for 64 cpu tsunami
--HG--
extra : convert_revision : 3ceaaa998518ded8613bc64edc04cb9120fd3d15
Diffstat (limited to 'dev/tsunamireg.h')
| -rw-r--r-- | dev/tsunamireg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 876c6bf18..3304082a5 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -60,6 +60,13 @@ #define TSDEV_CC_IIC2 0x1C #define TSDEV_CC_IIC3 0x1D +// BigTsunami Registers +#define TSDEV_CC_BDIMS 0x1000000 +#define TSDEV_CC_BDIRS 0x2000000 +#define TSDEV_CC_IPIQ 0x20 //0xf01a000800 +#define TSDEV_CC_IPIR 0x21 //0xf01a000840 +#define TSDEV_CC_ITIR 0x22 //0xf01a000880 + // PChip Registers #define TSDEV_PC_WSBA0 0x00 |