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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-06-10 13:30:58 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-06-10 13:30:58 -0400 |
| commit | 02f69b94c540a6b116c1a71a97f16facd21a5c44 (patch) | |
| tree | 7141d773d09c16f15b6785d5f6420129f7279c5f /dev/tsunamireg.h | |
| parent | a20f44979afd2a77d8b699534a4029d1e35464de (diff) | |
| download | gem5-02f69b94c540a6b116c1a71a97f16facd21a5c44.tar.xz | |
Fixes for detailed boot, made cttz and ctlz instructions more compact,
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
Diffstat (limited to 'dev/tsunamireg.h')
| -rw-r--r-- | dev/tsunamireg.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 58d5b63e1..2e4e873a0 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -132,10 +132,11 @@ #define RTC_CONTROL_REGISTERD 13 // control register D #define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 -#define PCHIP_PCI0_MEMORY ULL(0x10000000000) -#define PCHIP_PCI0_IO ULL(0x101FC000000) -#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY -#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO +#define PCHIP_PCI0_MEMORY ULL(0x00000000000) +#define PCHIP_PCI0_IO ULL(0x001FC000000) +#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) +#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY +#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO // UART Defines |