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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-02-05 15:12:33 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-02-05 15:12:33 -0500 |
| commit | 77a30ed48daec8fa8db2aaf955eda4e2384df912 (patch) | |
| tree | 8170250aca0261919bf38e1d1648886f5be398c0 /dev/tsunamireg.h | |
| parent | 09c40bfe4376d12b933116e17b8175f34a194f67 (diff) | |
| download | gem5-77a30ed48daec8fa8db2aaf955eda4e2384df912.tar.xz | |
fixed mapping of device memory and i/o space
--HG--
extra : convert_revision : 9236c7f0aeb4d555880bdfdfa7f55cedf1cbb950
Diffstat (limited to 'dev/tsunamireg.h')
| -rw-r--r-- | dev/tsunamireg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 7201edf94..c74279ecf 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -2,6 +2,8 @@ #ifndef __TSUNAMIREG_H__ #define __TSUNAMIREG_H__ +#define ALPHA_K0SEG_BASE 0xfffffc0000000000 + // CChip Registers #define TSDEV_CC_CSR 0x00 #define TSDEV_CC_MTR 0x01 @@ -99,5 +101,10 @@ #define RTC_CONTROL_REGISTERD 13 // control register D #define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 +#define PCHIP_PCI0_MEMORY 0x10000000000 +#define PCHIP_PCI0_IO 0x101FC000000 +#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY +#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO + #endif // __TSUNAMIREG_H__ |