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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-05-14 17:34:15 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-05-14 17:34:15 -0400 |
| commit | fd21387149c272b8aaee62466fe96863f3ef458f (patch) | |
| tree | e7029f7536b5374fc0fb5a9688d8d1a2b5a816b3 /dev/tsunamireg.h | |
| parent | cd8db7669aefe1075c9ded5e6cc3203593698880 (diff) | |
| download | gem5-fd21387149c272b8aaee62466fe96863f3ef458f.tar.xz | |
Linux boots... various fixes to make console work correctly
dev/console.cc:
commented out code that checks if an interrupt is happening before issuing one
because they can get lost when linux boots
dev/console.hh:
added a setPlatform function to set the platform to interrupt
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
Added virtual functions to post console interrupts
dev/tsunami_io.cc:
allowed a 64bit read of the PIC since we can't do a physical byte read
dev/tsunami_uart.cc:
moved TsunamiUart to PioDevice
various little fixes to make linux work
dev/tsunami_uart.hh:
Made Tsunami_Uart a PIO device
dev/tsunamireg.h:
added some UART defines and used the ULL macros
kern/linux/linux_system.cc:
commented out waiting for gdb
--HG--
extra : convert_revision : 8cfd0700f3812ab349a6d7f132f85f4f421c5c5e
Diffstat (limited to 'dev/tsunamireg.h')
| -rw-r--r-- | dev/tsunamireg.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 1207ebf9f..927dd60c9 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -70,6 +70,10 @@ // I/O Ports #define TSDEV_PIC1_MASK 0x21 #define TSDEV_PIC2_MASK 0xA1 +#define TSDEV_PIC1_ISR 0x20 +#define TSDEV_PIC2_ISR 0xA0 +#define TSDEV_PIC1_ACK 0x20 +#define TSDEV_PIC2_ACK 0xA0 #define TSDEV_DMA1_RESET 0x0D #define TSDEV_DMA2_RESET 0xDA #define TSDEV_DMA1_MODE 0x0B @@ -101,10 +105,16 @@ #define RTC_CONTROL_REGISTERD 13 // control register D #define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1 -#define PCHIP_PCI0_MEMORY 0x10000000000ULL -#define PCHIP_PCI0_IO 0x101FC000000ULL +#define PCHIP_PCI0_MEMORY ULL(0x10000000000) +#define PCHIP_PCI0_IO ULL(0x101FC000000) #define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY #define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO +// UART Defines + + +#define UART_IER_THRI 0x02 +#define UART_IER_RLSI 0x04 + #endif // __TSUNAMIREG_H__ |