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author | Miguel Serrano <mserrano@umich.edu> | 2005-08-15 16:59:58 -0400 |
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committer | Miguel Serrano <mserrano@umich.edu> | 2005-08-15 16:59:58 -0400 |
commit | b64eae5e52d9eb60ad498464d076b48cd5ceafe3 (patch) | |
tree | ba02beaf1c9ac36a344173cf48dab15545d20028 /dev/tsunamireg.h | |
parent | 1e2c16c9124ed3f51229daa715a6c00c2b97f73d (diff) | |
download | gem5-b64eae5e52d9eb60ad498464d076b48cd5ceafe3.tar.xz |
Changes for getting FreeBSD to run.
SConscript:
Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
Replaced htoa() with gtoh().
dev/disk_image.cc:
Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
Got rid of magic numbers.
Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
Got rid of unnecessary macros.
Changed RegType_t to IdeRegType.
Changed bmi_regs to allow accessing registers by name instead of just by array index.
Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
Made ReadConfig and WriteConfig begin with a lower-case letter.
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
Added classes for RTC and PIT modules.
dev/tsunamireg.h:
Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
Got rid of a magic number.
Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
Replaced htoa() with htog().
python/m5/objects/Pci.py:
PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
TsunamiFake was renamed as IsaFake.
sim/system.cc:
Replaced htoa()s with htog()s.
dev/isa_fake.cc:
New BitKeeper file ``dev/isa_fake.cc''
TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
New BitKeeper file ``dev/isa_fake.hh''
TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
New BitKeeper file ``dev/pitreg.h''
Useful macros for working with PIT (Periodic Interval Timer) registers.
--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
Diffstat (limited to 'dev/tsunamireg.h')
-rw-r--r-- | dev/tsunamireg.h | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h index 5fbfd5c31..583ff78b4 100644 --- a/dev/tsunamireg.h +++ b/dev/tsunamireg.h @@ -118,10 +118,18 @@ #define TSDEV_DMA2_MODE 0xD6 #define TSDEV_DMA1_MASK 0x0A #define TSDEV_DMA2_MASK 0xD4 -#define TSDEV_TMR_CTL 0x61 -#define TSDEV_TMR2_CTL 0x43 -#define TSDEV_TMR2_DATA 0x42 +#define TSDEV_CTRL_PORTB 0x61 #define TSDEV_TMR0_DATA 0x40 +#define TSDEV_TMR1_DATA 0x41 +#define TSDEV_TMR2_DATA 0x42 +#define TSDEV_TMR_CTRL 0x43 +#define TSDEV_KBD 0x64 +#define TSDEV_DMA1_CMND 0x08 +#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND +#define TSDEV_DMA2_CMND 0xD0 +#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND +#define TSDEV_DMA1_MMASK 0x0F +#define TSDEV_DMA2_MMASK 0xDE #define TSDEV_RTC_ADDR 0x70 #define TSDEV_RTC_DATA 0x71 @@ -145,4 +153,7 @@ #define UART_MCR_LOOP 0x10 +// System Control PortB Status Bits +#define PORTB_SPKR_HIGH 0x20 + #endif // __TSUNAMIREG_H__ |