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authorAli Saidi <saidi@eecs.umich.edu>2006-04-06 14:57:51 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-04-06 14:57:51 -0400
commit6240f8c4bcf12e3367905adfba066bb14f79262a (patch)
treee2e80d694535522023114f20ce97419b2b2ee71e /dev/uart.cc
parentbb80f71f213625e0b33db5cf2256f93caf3d5967 (diff)
downloadgem5-6240f8c4bcf12e3367905adfba066bb14f79262a.tar.xz
fixes for newmem
ALPHA_FS finally compiles again SConscript: Use a couple more FS sources, still don't compile that much arch/alpha/faults.hh: the unimp fault should probably exist in nonfs too. dev/alpha_console.cc: dev/alpha_console.hh: dev/simconsole.cc: dev/simple_disk.cc: dev/simple_disk.hh: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: sim/process.cc: sim/system.cc: fixes for newmem dev/io_device.hh: a system pointer is probably useful for every device to have mem/bus.hh: mem/physical.cc: new address ranges function python/m5/objects/SimpleDisk.py: simple disk now has a system pointer rather than physmem directly --HG-- extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf
Diffstat (limited to 'dev/uart.cc')
-rw-r--r--dev/uart.cc32
1 files changed, 3 insertions, 29 deletions
diff --git a/dev/uart.cc b/dev/uart.cc
index b2eeb8e9f..4a9f2b505 100644
--- a/dev/uart.cc
+++ b/dev/uart.cc
@@ -27,39 +27,19 @@
*/
/** @file
- * Implements a 8250 UART
+ * Implements a base class for UARTs
*/
-#include <string>
-#include <vector>
-
-#include "base/inifile.hh"
-#include "base/str.hh" // for to_number
-#include "base/trace.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "dev/platform.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
-Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
- Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
- : PioDevice(name, p), addr(a), size(s), cons(c)
+Uart::Uart(Params *p)
+ : BasicPioDevice(p), platform(p->platform), cons(p->cons)
{
- mmu->add_child(this, RangeSize(addr, size));
-
-
- if (bus) {
- pioInterface = newPioInterface(name, hier, bus, this,
- &Uart::cacheAccess);
- pioInterface->addAddrRange(RangeSize(addr, size));
- pioLatency = pio_latency * bus->clockRate;
- }
status = 0;
@@ -68,11 +48,5 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
platform->uart = this;
}
-Tick
-Uart::cacheAccess(MemReqPtr &req)
-{
- return curTick + pioLatency;
-}
-
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)