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| author | Miguel Serrano <mserrano@umich.edu> | 2005-08-16 15:44:57 -0400 |
|---|---|---|
| committer | Miguel Serrano <mserrano@umich.edu> | 2005-08-16 15:44:57 -0400 |
| commit | 1906abcde04c7f9af8186ac1a8a726a9ea80936f (patch) | |
| tree | 7a6065bdf35209e5e39bf197f791b7eebb9180c5 /dev/uart8250.cc | |
| parent | b64eae5e52d9eb60ad498464d076b48cd5ceafe3 (diff) | |
| download | gem5-1906abcde04c7f9af8186ac1a8a726a9ea80936f.tar.xz | |
Uart fix.
dev/uart8250.cc:
Fixed implementation of "transmit interrupt clear".
--HG--
extra : convert_revision : cb69d61413ea799d5d3825fe2f0891dd72995561
Diffstat (limited to 'dev/uart8250.cc')
| -rw-r--r-- | dev/uart8250.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/dev/uart8250.cc b/dev/uart8250.cc index bbde14769..2ad020462 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -147,13 +147,15 @@ Uart8250::read(MemReqPtr &req, uint8_t *data) case 0x2: // Intr Identification Register (IIR) DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status); - //Tx interrupts are cleared on IIR reads - status &= ~TX_INT; - - if (status & RX_INT) + if (status & RX_INT) /* Rx data interrupt has a higher priority */ *(uint8_t*)data = IIR_RXID; + else if (status & TX_INT) + *(uint8_t*)data = IIR_TXID; else *(uint8_t*)data = IIR_NOPEND; + + //Tx interrupts are cleared on IIR reads + status &= ~TX_INT; break; case 0x3: // Line Control Register (LCR) *(uint8_t*)data = LCR; |