fs now gets to the point where it would really like a filesystem.

Time to make the ide device work

arch/alpha/system.cc:
    write the machine type and rev in the correct place
cpu/simple/cpu.cc:
    reset the packet structure every time it's reused... wow the
    simple cpu code  for talking to memory is getting horrible.
dev/alpha_console.cc:
    move the setAlphaAccess to startup() to make sure that the console
    binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
    fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
    More verbose bus tracing
mem/packet.hh:
    Add a constructor to packet to set the result to unknown and a reset
    method in the case it's being reused
mem/vport.hh:
    don't need are own read/write methods since the base functional port
    ones call writeBlob readBlob which do the translation for us

--HG--
extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a

1 files changed, 6 insertions, 2 deletions

diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index 7c8899180..7e2f9d51f 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -111,7 +111,7 @@ Tick
 Uart8250::read(Packet &pkt)
 {
     assert(pkt.result == Unknown);
-    assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
+    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
     assert(pkt.size == 1);
 
     pkt.time = curTick + pioDelay;
@@ -189,7 +189,10 @@ Uart8250::read(Packet &pkt)
             panic("Tried to access a UART port that doesn't exist\n");
             break;
     }
-
+/*    uint32_t d32 = *data;
+    DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
+*/
+    pkt.result = Success;
     return pioDelay;
 }
 
@@ -269,6 +272,7 @@ Uart8250::write(Packet &pkt)
             panic("Tried to access a UART port that doesn't exist\n");
             break;
     }
+    pkt.result = Success;
     return pioDelay;
 }