fixes for newmem

ALPHA_FS finally compiles again

SConscript:
    Use a couple more FS sources, still don't compile that much
arch/alpha/faults.hh:
    the unimp fault should probably exist in nonfs too.
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/simconsole.cc:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
sim/process.cc:
sim/system.cc:
    fixes for newmem
dev/io_device.hh:
    a system pointer is probably useful for every device to have
mem/bus.hh:
mem/physical.cc:
    new address ranges function
python/m5/objects/SimpleDisk.py:
    simple disk now has a system pointer rather than physmem directly

--HG--
extra : convert_revision : d8c0a5c6510a6210aec5e8adfb0a4a06ec0dcebf

1 files changed, 6 insertions, 8 deletions

diff --git a/dev/uart8250.hh b/dev/uart8250.hh
index 63d1da3cf..76b17caf8 100644
--- a/dev/uart8250.hh
+++ b/dev/uart8250.hh
@@ -30,8 +30,8 @@
  * Defines a 8250 UART
  */
 
-#ifndef __TSUNAMI_UART_HH__
-#define __TSUNAMI_UART_HH__
+#ifndef __DEV_UART8250_HH__
+#define __DEV_UART8250_HH__
 
 #include "dev/tsunamireg.h"
 #include "base/range.hh"
@@ -53,7 +53,6 @@
 #define IIR_LINE  0x06 /* Rx Line Status (highest priority)*/
 
 class SimConsole;
-class MemoryController;
 class Platform;
 
 class Uart8250 : public Uart
@@ -79,12 +78,11 @@ class Uart8250 : public Uart
     IntrEvent rxIntrEvent;
 
   public:
-    Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
-         Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
-         Platform *p);
+    Uart8250(Params *p);
 
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Tick read(Packet &pkt);
+    virtual Tick write(Packet &pkt);
+    virtual void addressRanges(AddrRangeList &range_list);
 
 
     /**