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authorGabe Black <gblack@eecs.umich.edu>2006-04-06 15:00:11 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-04-06 15:00:11 -0400
commit6a962f8343d0e7f138baa4034633c986eecc9edf (patch)
treef16fdcc7455b0e7cd14af660ebdeb029db3c669a /dev/uart8250.hh
parent3124c5b7bb0cdcb3b16b52533c6a3e50a5970152 (diff)
parent6240f8c4bcf12e3367905adfba066bb14f79262a (diff)
downloadgem5-6a962f8343d0e7f138baa4034633c986eecc9edf.tar.xz
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : bd6352647798275a12d52d55a129cdddd8e25423
Diffstat (limited to 'dev/uart8250.hh')
-rw-r--r--dev/uart8250.hh14
1 files changed, 6 insertions, 8 deletions
diff --git a/dev/uart8250.hh b/dev/uart8250.hh
index 63d1da3cf..76b17caf8 100644
--- a/dev/uart8250.hh
+++ b/dev/uart8250.hh
@@ -30,8 +30,8 @@
* Defines a 8250 UART
*/
-#ifndef __TSUNAMI_UART_HH__
-#define __TSUNAMI_UART_HH__
+#ifndef __DEV_UART8250_HH__
+#define __DEV_UART8250_HH__
#include "dev/tsunamireg.h"
#include "base/range.hh"
@@ -53,7 +53,6 @@
#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
class SimConsole;
-class MemoryController;
class Platform;
class Uart8250 : public Uart
@@ -79,12 +78,11 @@ class Uart8250 : public Uart
IntrEvent rxIntrEvent;
public:
- Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
- Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
- Platform *p);
+ Uart8250(Params *p);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Tick read(Packet &pkt);
+ virtual Tick write(Packet &pkt);
+ virtual void addressRanges(AddrRangeList &range_list);
/**