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authorAli Saidi <saidi@eecs.umich.edu>2004-10-25 18:15:28 -0400
committerAli Saidi <saidi@eecs.umich.edu>2004-10-25 18:15:28 -0400
commitbe0184b463056645d97598dfc98292f75e579b1a (patch)
tree9d780c3c804b42fc40e680994ff248af4c4b58c3 /dev
parentd55eb90fc73e27d26e64daa4c69efc3beee00429 (diff)
parent3402411661caff075890c20a6c59fa471d5e68ac (diff)
downloadgem5-be0184b463056645d97598dfc98292f75e579b1a.tar.xz
Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smp
--HG-- extra : convert_revision : 59173b5d4599cfe1cbaa96705e9731ee5a8d8647
Diffstat (limited to 'dev')
-rw-r--r--dev/ide_ctrl.cc4
-rw-r--r--dev/ide_disk.cc2
-rw-r--r--dev/ns_gige.cc4
-rw-r--r--dev/platform.hh2
-rw-r--r--dev/tsunami.cc12
-rw-r--r--dev/tsunami.hh10
6 files changed, 30 insertions, 4 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 787049533..d08e61fbf 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -242,13 +242,13 @@ IdeController::setDmaComplete(IdeDisk *disk)
void
IdeController::intrPost()
{
- tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
}
void
IdeController::intrClear()
{
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
}
////
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index 405b77eca..f3760bd5e 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -732,6 +732,7 @@ IdeDisk::startCommand()
void
IdeDisk::intrPost()
{
+ DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n");
if (intrPending)
panic("Attempt to post an interrupt with one pending\n");
@@ -745,6 +746,7 @@ IdeDisk::intrPost()
void
IdeDisk::intrClear()
{
+ DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n");
if (!intrPending)
panic("Attempt to clear a non-pending interrupt\n");
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 2b19cebe9..4d0b93ab9 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -1029,7 +1029,7 @@ NSGigE::cpuInterrupt()
cpuPendingIntr = true;
DPRINTF(EthernetIntr, "posting cchip interrupt\n");
- tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
}
}
@@ -1049,7 +1049,7 @@ NSGigE::cpuIntrClear()
cpuPendingIntr = false;
DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
+ tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
}
bool
diff --git a/dev/platform.hh b/dev/platform.hh
index 7920480bc..0c90e06ba 100644
--- a/dev/platform.hh
+++ b/dev/platform.hh
@@ -65,6 +65,8 @@ class Platform : public SimObject
virtual void postConsoleInt() = 0;
virtual void clearConsoleInt() = 0;
virtual Tick intrFrequency() = 0;
+ virtual void postPciInt(int line) = 0;
+ virtual void clearPciInt(int line) = 0;
};
#endif // __PLATFORM_HH_
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index c44da69b7..ce2d473a9 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -75,6 +75,18 @@ Tsunami::clearConsoleInt()
}
void
+Tsunami::postPciInt(int line)
+{
+ this->cchip->postDRIR(line);
+}
+
+void
+Tsunami::clearPciInt(int line)
+{
+ this->cchip->clearDRIR(line);
+}
+
+void
Tsunami::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 4367383ff..0a7fdbcd9 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -109,6 +109,16 @@ class Tsunami : public Platform
virtual void clearConsoleInt();
/**
+ * Cause the chipset to post a cpi interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+ /**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/