Mostly IO modifications, to increase compatibility with FreeBSD.

dev/pcidev.cc:
    Allow writes to some PCI read-only registers.
    Fix problem when writing to a zero offset IO location.
dev/tsunami_io.cc:
    Fix calculation of IO addresses.
    Add registers for keyboard and PCI DMA.
dev/tsunamireg.h:
    Add registers for keyboard and PCI DMA.
python/m5/objects/System.py:
    Allow generic System to be instantiated.

--HG--
extra : convert_revision : 1b985ffa2b8e15aa55246f1d14da615c32ecd3f9

3 files changed, 36 insertions, 4 deletions

diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index f2bce33ca..93200a8c7 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -138,7 +138,13 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
           case PCI_LATENCY_TIMER:
             *(uint8_t *)&config.data[offset] = htoa(byte_value);
             break;
-
+          /* Do nothing for these read-only registers */
+          case PCI0_INTERRUPT_PIN:
+          case PCI0_MINIMUM_GRANT:
+          case PCI0_MAXIMUM_LATENCY:
+          case PCI_CLASS_CODE:
+          case PCI_REVISION_ID:
+            break;
           default:
             panic("writing to a read only register");
         }
@@ -192,7 +198,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
                         htoa((word_value & ~0x3) |
                         (htoa(config.data[offset]) & 0x3));
 
-                    if (word_value & ~0x1) {
+                    if (word_value != 0x1) {
                         Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
                         Addr base_size = BARSize[barnum];
 
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index da1062237..5d5eba68e 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -207,12 +207,16 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
     DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n",
             req->vaddr, req->size, req->vaddr & 0xfff);
 
-    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
+    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20;
 
 
     switch(req->size) {
       case sizeof(uint8_t):
         switch(daddr) {
+          // PIC1 mask read
+          case TSDEV_PIC1_MASK:
+            *(uint8_t*)data = ~mask1;
+            return No_Fault;
           case TSDEV_PIC1_ISR:
               // !!! If this is modified 64bit case needs to be too
               // Pal code has to do a 64 bit physical read because there is
@@ -267,6 +271,14 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
                 panic("Unknown RTC Address\n");
             }
 
+          /* Added for keyboard reads */
+          case TSDEV_KBD:
+            *(uint8_t *)data = 0x00;
+            return No_Fault;
+          /* Added for ATA PCI DMA */
+          case ATA_PCI_DMA:
+            *(uint8_t *)data = 0x00;
+            return No_Fault;
           default:
             panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
         }
@@ -309,7 +321,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
     DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
             req->vaddr, req->size, req->vaddr & 0xfff, dt64);
 
-    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
+    Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) + 0x20;
 
     switch(req->size) {
       case sizeof(uint8_t):
@@ -396,6 +408,8 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
           case TSDEV_RTC_ADDR:
             RTCAddress = *(uint8_t*)data;
             return No_Fault;
+          case TSDEV_KBD:
+            return No_Fault;
           case TSDEV_RTC_DATA:
             panic("RTC Write not implmented (rtc.o won't work)\n");
           default:
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h
index 5fbfd5c31..8b290deb1 100644
--- a/dev/tsunamireg.h
+++ b/dev/tsunamireg.h
@@ -123,6 +123,18 @@
 #define TSDEV_TMR2_DATA     0x42
 #define TSDEV_TMR0_DATA     0x40
 
+/* Added for keyboard accesses */
+#define TSDEV_KBD           0x64
+
+/* Added for ATA PCI DMA */
+#define ATA_PCI_DMA         0x00
+#define ATA_PCI_DMA2        0x02
+#define ATA_PCI_DMA3        0x16
+#define ATA_PCI_DMA4        0x17
+#define ATA_PCI_DMA5        0x1a
+#define ATA_PCI_DMA6        0x11
+#define ATA_PCI_DMA7        0x14
+
 #define TSDEV_RTC_ADDR      0x70
 #define TSDEV_RTC_DATA      0x71