Use parameter structs for initialization so it's easier

to add new devices.  Abstract the Platform more so that
it is unnecessary to know know platform specifics for
interrupting or translating PCI DMA addresses.

dev/ide_ctrl.cc:
    convert to parameter struct for initialization
    use the interrupt functions in the PciDev base class
    convert from tsunami to using platform
    We don't need an interrupt controller here.
dev/ide_ctrl.hh:
    don't use Tsunami, use Platform
    make the IdeDisk a friend so that it can access my plaform
    convert to parameter struct for construction
dev/ide_disk.cc:
    don't use tsunami references, but platform references
dev/ns_gige.cc:
    Convert to parameter struct for initialzation. Use code in
    base class for interrupts so we don't need to know anything
    about the platform. Don't need an IntrControl *.
dev/ns_gige.hh:
    We don't need a Tsunami * anymore
    convert to a parameter struct for construction
dev/pcidev.cc:
    deal with new parameter struct
dev/pcidev.hh:
    - Move all of the configuration parameters into a param struct
    that we can pass into the constructor.
    - Add a Platform * for accessing new generic interrupt post/clear
    and dma address translation fuctions
    - Create functions for posting/clearing interrupts and translating
    dma addresses
dev/platform.cc:
    have default functions that panic on pci calls
dev/platform.hh:
    don't make the pci stuff pure virtual, but rather provide
    default implementations that panic.  Also, add dma address
    translation.
dev/tsunami.cc:
    this-> isn't necessary here.
    add pci address translation
dev/tsunami.hh:
    implement the pciToDma address translation

--HG--
extra : convert_revision : 7db27a2fa1f1bd84704921ec7ca0280b5653c43e

11 files changed, 248 insertions, 191 deletions

diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index aa0217745..109908ead 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -39,7 +39,6 @@
 #include "dev/pciconfigall.hh"
 #include "dev/pcireg.h"
 #include "dev/platform.hh"
-#include "dev/tsunami_cchip.hh"
 #include "mem/bus/bus.hh"
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
@@ -55,13 +54,8 @@ using namespace std;
 // Initialization and destruction
 ////
 
-IdeController::IdeController(const string &name, IntrControl *ic,
-                             const vector<IdeDisk *> &new_disks,
-                             MemoryController *mmu, PciConfigAll *cf,
-                             PciConfigData *cd, Tsunami *t, uint32_t bus_num,
-                             uint32_t dev_num, uint32_t func_num,
-                             Bus *host_bus, Tick pio_latency, HierParams *hier)
-    : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
+IdeController::IdeController(Params *p)
+    : PciDev(p)
 {
     // initialize the PIO interface addresses
     pri_cmd_addr = 0;
@@ -96,23 +90,25 @@ IdeController::IdeController(const string &name, IntrControl *ic,
     memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
 
     // create the PIO and DMA interfaces
-    if (host_bus) {
-        pioInterface = newPioInterface(name, hier, host_bus, this,
+    if (params()->host_bus) {
+        pioInterface = newPioInterface(name(), params()->hier,
+                                       params()->host_bus, this,
                                        &IdeController::cacheAccess);
 
-        dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
-                                             host_bus, 1);
-        pioLatency = pio_latency * host_bus->clockRatio;
+        dmaInterface = new DMAInterface<Bus>(name() + ".dma",
+                                             params()->host_bus,
+                                             params()->host_bus, 1);
+        pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
     }
 
     // setup the disks attached to controller
     memset(disks, 0, sizeof(IdeDisk *) * 4);
 
-    if (new_disks.size() > 3)
+    if (params()->disks.size() > 3)
         panic("IDE controllers support a maximum of 4 devices attached!\n");
 
-    for (int i = 0; i < new_disks.size(); i++) {
-        disks[i] = new_disks[i];
+    for (int i = 0; i < params()->disks.size(); i++) {
+        disks[i] = params()->disks[i];
         disks[i]->setController(this, dmaInterface);
     }
 }
@@ -236,22 +232,6 @@ IdeController::setDmaComplete(IdeDisk *disk)
 }
 
 ////
-// Interrupt handling
-////
-
-void
-IdeController::intrPost()
-{
-    tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
-}
-
-void
-IdeController::intrClear()
-{
-    tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
-}
-
-////
 // Bus timing and bus access functions
 ////
 
@@ -684,12 +664,11 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 
-    SimObjectParam<IntrControl *> intr_ctrl;
     SimObjectVectorParam<IdeDisk *> disks;
     SimObjectParam<MemoryController *> mmu;
     SimObjectParam<PciConfigAll *> configspace;
     SimObjectParam<PciConfigData *> configdata;
-    SimObjectParam<Tsunami *> tsunami;
+    SimObjectParam<Platform *> platform;
     Param<uint32_t> pci_bus;
     Param<uint32_t> pci_dev;
     Param<uint32_t> pci_func;
@@ -701,12 +680,11 @@ END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
 
-    INIT_PARAM(intr_ctrl, "Interrupt Controller"),
     INIT_PARAM(disks, "IDE disks attached to this controller"),
     INIT_PARAM(mmu, "Memory controller"),
     INIT_PARAM(configspace, "PCI Configspace"),
     INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(tsunami, "Tsunami chipset pointer"),
+    INIT_PARAM(platform, "Platform pointer"),
     INIT_PARAM(pci_bus, "PCI bus ID"),
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
@@ -718,9 +696,21 @@ END_INIT_SIM_OBJECT_PARAMS(IdeController)
 
 CREATE_SIM_OBJECT(IdeController)
 {
-    return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
-                             configspace, configdata, tsunami, pci_bus,
-                             pci_dev, pci_func, io_bus, pio_latency, hier);
+    IdeController::Params *params = new IdeController::Params;
+    params->name = getInstanceName();
+    params->mmu = mmu;
+    params->configSpace = configspace;
+    params->configData = configdata;
+    params->plat = platform;
+    params->busNum = pci_bus;
+    params->deviceNum = pci_dev;
+    params->functionNum = pci_func;
+
+    params->disks = disks;
+    params->host_bus = io_bus;
+    params->pio_latency = pio_latency;
+    params->hier = hier;
+    return new IdeController(params);
 }
 
 REGISTER_SIM_OBJECT("IdeController", IdeController)
diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index b29e5ae9a..9a6b476b8 100644
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -80,14 +80,14 @@ typedef enum RegType {
     BMI_BLOCK
 } RegType_t;
 
+class BaseInterface;
+class Bus;
+class HierParams;
 class IdeDisk;
 class IntrControl;
 class PciConfigAll;
-class Tsunami;
 class PhysicalMemory;
-class BaseInterface;
-class HierParams;
-class Bus;
+class Platform;
 
 /**
  * Device model for an Intel PIIX4 IDE controller
@@ -95,6 +95,8 @@ class Bus;
 
 class IdeController : public PciDev
 {
+    friend class IdeDisk;
+
   private:
     /** Primary command block registers */
     Addr pri_cmd_addr;
@@ -125,10 +127,6 @@ class IdeController : public PciDev
     bool bm_enabled;
     bool cmd_in_progress[4];
 
-  public:
-    /** Pointer to the chipset */
-    Tsunami *tsunami;
-
   private:
     /** IDE disks connected to controller */
     IdeDisk *disks[4];
@@ -149,29 +147,18 @@ class IdeController : public PciDev
     bool isDiskSelected(IdeDisk *diskPtr);
 
   public:
-    /**
-     * Constructs and initializes this controller.
-     * @param name The name of this controller.
-     * @param ic The interrupt controller.
-     * @param mmu The memory controller
-     * @param cf PCI config space
-     * @param cd PCI config data
-     * @param bus_num The PCI bus number
-     * @param dev_num The PCI device number
-     * @param func_num The PCI function number
-     * @param host_bus The host bus to connect to
-     * @param hier The hierarchy parameters
-     */
-    IdeController(const std::string &name, IntrControl *ic,
-                  const std::vector<IdeDisk *> &new_disks,
-                  MemoryController *mmu, PciConfigAll *cf,
-                  PciConfigData *cd, Tsunami *t,
-                  uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
-                  Bus *host_bus, Tick pio_latency, HierParams *hier);
+    struct Params : public PciDev::Params
+    {
+        /** Array of disk objects */
+        std::vector<IdeDisk *> disks;
+        Bus *host_bus;
+        Tick pio_latency;
+        HierParams *hier;
+    };
+    const Params *params() const { return (const Params *)_params; }
 
-    /**
-     * Deletes the connected devices.
-     */
+  public:
+    IdeController(Params *p);
     ~IdeController();
 
     virtual void WriteConfig(int offset, int size, uint32_t data);
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index f3760bd5e..073c10436 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -177,7 +177,7 @@ Addr
 IdeDisk::pciToDma(Addr pciAddr)
 {
     if (ctrl)
-        return ctrl->tsunami->pchip->translatePciToDma(pciAddr);
+        return ctrl->plat->pciToDma(pciAddr);
     else
         panic("Access to unset controller!\n");
 }
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 8eca91510..8f233c433 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -41,7 +41,6 @@
 #include "dev/etherlink.hh"
 #include "dev/ns_gige.hh"
 #include "dev/pciconfigall.hh"
-#include "dev/tsunami_cchip.hh"
 #include "mem/bus/bus.hh"
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
@@ -92,64 +91,62 @@ using namespace Net;
 //
 // NSGigE PCI Device
 //
-NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
-               PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
-               MemoryController *mmu, HierParams *hier, Bus *header_bus,
-               Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
-               bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
-               Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
-               PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
-               uint32_t func, bool rx_filter, EthAddr eaddr,
-               uint32_t tx_fifo_size, uint32_t rx_fifo_size)
-    : PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), ioEnable(false),
-      maxTxFifoSize(tx_fifo_size), maxRxFifoSize(rx_fifo_size),
+NSGigE::NSGigE(Params *p)
+    : PciDev(p), ioEnable(false),
+      txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
       txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
       txXferLen(0), rxXferLen(0), txState(txIdle), txEnable(false),
-      CTDD(false), txFifoAvail(tx_fifo_size),
+      CTDD(false),
       txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
-      rxEnable(false), CRDD(false), rxPktBytes(0), rxFifoCnt(0),
+      rxEnable(false), CRDD(false), rxPktBytes(0),
       rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
       rxDmaReadEvent(this), rxDmaWriteEvent(this),
       txDmaReadEvent(this), txDmaWriteEvent(this),
-      dmaDescFree(dma_desc_free), dmaDataFree(dma_data_free),
-      txDelay(tx_delay), rxDelay(rx_delay), rxKickTick(0), txKickTick(0),
-      txEvent(this), rxFilterEnable(rx_filter), acceptBroadcast(false),
+      dmaDescFree(p->dma_desc_free), dmaDataFree(p->dma_data_free),
+      txDelay(p->tx_delay), rxDelay(p->rx_delay),
+      rxKickTick(0), txKickTick(0),
+      txEvent(this), rxFilterEnable(p->rx_filter), acceptBroadcast(false),
       acceptMulticast(false), acceptUnicast(false),
       acceptPerfect(false), acceptArp(false),
-      physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false),
+      physmem(p->pmem), intrTick(0), cpuPendingIntr(false),
       intrEvent(0), interface(0)
 {
-    if (header_bus) {
-        pioInterface = newPioInterface(name, hier, header_bus, this,
+    if (p->header_bus) {
+        pioInterface = newPioInterface(name(), p->hier,
+                                       p->header_bus, this,
                                        &NSGigE::cacheAccess);
 
-        pioLatency = pio_latency * header_bus->clockRatio;
+        pioLatency = p->pio_latency * p->header_bus->clockRatio;
 
-        if (payload_bus)
-            dmaInterface = new DMAInterface<Bus>(name + ".dma",
-                                                 header_bus, payload_bus, 1);
+        if (p->payload_bus)
+            dmaInterface = new DMAInterface<Bus>(name() + ".dma",
+                                                 p->header_bus,
+                                                 p->payload_bus, 1);
         else
-            dmaInterface = new DMAInterface<Bus>(name + ".dma",
-                                                 header_bus, header_bus, 1);
-    } else if (payload_bus) {
-        pioInterface = newPioInterface(name, hier, payload_bus, this,
+            dmaInterface = new DMAInterface<Bus>(name() + ".dma",
+                                                 p->header_bus,
+                                                 p->header_bus, 1);
+    } else if (p->payload_bus) {
+        pioInterface = newPioInterface(name(), p->hier,
+                                       p->payload_bus, this,
                                        &NSGigE::cacheAccess);
 
-        pioLatency = pio_latency * payload_bus->clockRatio;
+        pioLatency = p->pio_latency * p->payload_bus->clockRatio;
 
-        dmaInterface = new DMAInterface<Bus>(name + ".dma", payload_bus,
-                                         payload_bus, 1);
+        dmaInterface = new DMAInterface<Bus>(name() + ".dma",
+                                             p->payload_bus,
+                                             p->payload_bus, 1);
     }
 
 
-    intrDelay = US2Ticks(intr_delay);
-    dmaReadDelay = dma_read_delay;
-    dmaWriteDelay = dma_write_delay;
-    dmaReadFactor = dma_read_factor;
-    dmaWriteFactor = dma_write_factor;
+    intrDelay = US2Ticks(p->intr_delay);
+    dmaReadDelay = p->dma_read_delay;
+    dmaWriteDelay = p->dma_write_delay;
+    dmaReadFactor = p->dma_read_factor;
+    dmaWriteFactor = p->dma_write_factor;
 
     regsReset();
-    memcpy(&rom.perfectMatch, eaddr.bytes(), ETH_ADDR_LEN);
+    memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN);
 }
 
 NSGigE::~NSGigE()
@@ -1028,8 +1025,8 @@ NSGigE::cpuInterrupt()
         // Send interrupt
         cpuPendingIntr = true;
 
-        DPRINTF(EthernetIntr, "posting cchip interrupt\n");
-        tsunami->postPciInt(configData->config.hdr.pci0.interruptLine);
+        DPRINTF(EthernetIntr, "posting interrupt\n");
+        intrPost();
     }
 }
 
@@ -1048,8 +1045,8 @@ NSGigE::cpuIntrClear()
 
     cpuPendingIntr = false;
 
-    DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
-    tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine);
+    DPRINTF(EthernetIntr, "clearing interrupt\n");
+    intrClear();
 }
 
 bool
@@ -2450,7 +2447,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
     Param<Tick> tx_delay;
     Param<Tick> rx_delay;
-    SimObjectParam<IntrControl *> intr_ctrl;
     Param<Tick> intr_delay;
     SimObjectParam<MemoryController *> mmu;
     SimObjectParam<PhysicalMemory *> physmem;
@@ -2468,7 +2464,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<Tick> dma_write_factor;
     SimObjectParam<PciConfigAll *> configspace;
     SimObjectParam<PciConfigData *> configdata;
-    SimObjectParam<Tsunami *> tsunami;
+    SimObjectParam<Platform *> platform;
     Param<uint32_t> pci_bus;
     Param<uint32_t> pci_dev;
     Param<uint32_t> pci_func;
@@ -2481,7 +2477,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
     INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
     INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
-    INIT_PARAM(intr_ctrl, "Interrupt Controller"),
     INIT_PARAM_DFLT(intr_delay, "Interrupt Delay in microseconds", 0),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(physmem, "Physical Memory"),
@@ -2500,7 +2495,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
     INIT_PARAM(configspace, "PCI Configspace"),
     INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(tsunami, "Tsunami"),
+    INIT_PARAM(platform, "Platform"),
     INIT_PARAM(pci_bus, "PCI bus"),
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
@@ -2512,14 +2507,36 @@ END_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
 CREATE_SIM_OBJECT(NSGigE)
 {
-    return new NSGigE(getInstanceName(), intr_ctrl, intr_delay,
-                      physmem, tx_delay, rx_delay, mmu, hier, header_bus,
-                      payload_bus, pio_latency, dma_desc_free, dma_data_free,
-                      dma_read_delay, dma_write_delay, dma_read_factor,
-                      dma_write_factor, configspace, configdata,
-                      tsunami, pci_bus, pci_dev, pci_func, rx_filter,
-                      EthAddr((string)hardware_address),
-                      tx_fifo_size, rx_fifo_size);
+    NSGigE::Params *params = new NSGigE::Params;
+
+    params->name = getInstanceName();
+    params->mmu = mmu;
+    params->configSpace = configspace;
+    params->configData = configdata;
+    params->plat = platform;
+    params->busNum = pci_bus;
+    params->deviceNum = pci_dev;
+    params->functionNum = pci_func;
+
+    params->intr_delay = intr_delay;
+    params->pmem = physmem;
+    params->tx_delay = tx_delay;
+    params->rx_delay = rx_delay;
+    params->hier = hier;
+    params->header_bus = header_bus;
+    params->payload_bus = payload_bus;
+    params->pio_latency = pio_latency;
+    params->dma_desc_free = dma_desc_free;
+    params->dma_data_free = dma_data_free;
+    params->dma_read_delay = dma_read_delay;
+    params->dma_write_delay = dma_write_delay;
+    params->dma_read_factor = dma_read_factor;
+    params->dma_write_factor = dma_write_factor;
+    params->rx_filter = rx_filter;
+    params->eaddr = hardware_address;
+    params->tx_fifo_size = tx_fifo_size;
+    params->rx_fifo_size = rx_fifo_size;
+    return new NSGigE(params);
 }
 
 REGISTER_SIM_OBJECT("NSGigE", NSGigE)
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 60dcf3fc2..5f023dccc 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -41,7 +41,6 @@
 #include "dev/io_device.hh"
 #include "dev/ns_gige_reg.h"
 #include "dev/pcidev.hh"
-#include "dev/tsunami.hh"
 #include "mem/bus/bus.hh"
 #include "sim/eventq.hh"
 
@@ -139,10 +138,6 @@ class NSGigE : public PciDev
     };
 
   private:
-    /** pointer to the chipset */
-    Tsunami *tsunami;
-
-  private:
     Addr addr;
     static const Addr size = sizeof(dp_regs);
 
@@ -330,16 +325,31 @@ class NSGigE : public PciDev
     NSGigEInt *interface;
 
   public:
-    NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
-           PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
-           MemoryController *mmu, HierParams *hier, Bus *header_bus,
-           Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
-           bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
-           Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
-           PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
-           uint32_t func, bool rx_filter, Net::EthAddr eaddr,
-           uint32_t tx_fifo_size, uint32_t rx_fifo_size);
+    struct Params : public PciDev::Params
+    {
+        PhysicalMemory *pmem;
+        HierParams *hier;
+        Bus *header_bus;
+        Bus *payload_bus;
+        Tick intr_delay;
+        Tick tx_delay;
+        Tick rx_delay;
+        Tick pio_latency;
+        bool dma_desc_free;
+        bool dma_data_free;
+        Tick dma_read_delay;
+        Tick dma_write_delay;
+        Tick dma_read_factor;
+        Tick dma_write_factor;
+        bool rx_filter;
+        Net::EthAddr eaddr;
+        uint32_t tx_fifo_size;
+        uint32_t rx_fifo_size;
+    };
+
+    NSGigE(Params *params);
     ~NSGigE();
+    const Params *params() const { return (const Params *)_params; }
 
     virtual void WriteConfig(int offset, int size, uint32_t data);
     virtual void ReadConfig(int offset, int size, uint8_t *data);
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index f0ceb40f2..0c64bcb94 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -50,24 +50,23 @@
 
 using namespace std;
 
-PciDev::PciDev(const string &name, MemoryController *mmu, PciConfigAll *cf,
-               PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
-    : DmaDevice(name), mmu(mmu), configSpace(cf), configData(cd), busNum(bus),
-      deviceNum(dev), functionNum(func)
+PciDev::PciDev(Params *p)
+    : DmaDevice(p->name), _params(p), plat(p->plat), configData(p->configData)
 {
     // copy the config data from the PciConfigData object
-    if (cd) {
-        memcpy(config.data, cd->config.data, sizeof(config.data));
-        memcpy(BARSize, cd->BARSize, sizeof(BARSize));
-        memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
+    if (configData) {
+        memcpy(config.data, configData->config.data, sizeof(config.data));
+        memcpy(BARSize, configData->BARSize, sizeof(BARSize));
+        memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
     } else
         panic("NULL pointer to configuration data");
 
     // Setup pointer in config space to point to this entry
-    if (cf->deviceExists(dev,func))
-        panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
+    if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
+        panic("Two PCI devices occuping same dev: %#x func: %#x",
+              p->deviceNum, p->functionNum);
     else
-        cf->registerDevice(dev, func, this);
+        p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
 }
 
 void
@@ -79,7 +78,7 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
         *(uint32_t*)data = htoa(*(uint32_t*)data);
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
-                deviceNum, functionNum, offset, size,
+                params()->deviceNum, params()->functionNum, offset, size,
                 *(uint32_t*)(config.data + offset));
         break;
 
@@ -88,7 +87,7 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
         *(uint16_t*)data = htoa(*(uint16_t*)data);
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
-                deviceNum, functionNum, offset, size,
+                params()->deviceNum, params()->functionNum, offset, size,
                 *(uint16_t*)(config.data + offset));
         break;
 
@@ -96,7 +95,7 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
         memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
         DPRINTF(PCIDEV,
                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
-                deviceNum, functionNum, offset, size,
+                params()->deviceNum, params()->functionNum, offset, size,
                 (uint16_t)(*(uint8_t*)(config.data + offset)));
         break;
 
@@ -119,7 +118,8 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
 
     DPRINTF(PCIDEV,
             "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
-            deviceNum, functionNum, offset, size, word_value);
+            params()->deviceNum, params()->functionNum, offset, size,
+            word_value);
 
     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 
@@ -177,6 +177,8 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
                         (htoa(config.data[offset]) & 0xF));
                 }
             } else {
+                MemoryController *mmu = params()->mmu;
+
                 // This is I/O Space, bottom two bits are read only
                 if(htoa(config.data[offset]) & 0x1) {
                     *(uint32_t *)&config.data[offset] = htoa((word_value & ~0x3) |
@@ -265,7 +267,7 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
     // Add the MMU mappings for the BARs
     for (int i=0; i < 6; i++) {
         if (BARAddrs[i] != 0)
-            mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
+            params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
     }
 }
 
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index c0fe47ac4..73d2e3c44 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -30,11 +30,12 @@
  * Interface for devices using PCI configuration
  */
 
-#ifndef __PCI_DEV_HH__
-#define __PCI_DEV_HH__
+#ifndef __DEV_PCIDEV_HH__
+#define __DEV_PCIDEV_HH__
 
-#include "dev/pcireg.h"
 #include "dev/io_device.hh"
+#include "dev/pcireg.h"
+#include "dev/platform.hh"
 
 class PciConfigAll;
 class MemoryController;
@@ -78,29 +79,43 @@ class PciConfigData : public SimObject
 class PciDev : public DmaDevice
 {
   protected:
-    MemoryController *mmu;
-    /** A pointer to the configspace all object that calls
-     * us when a read comes to this particular device/function.
-     */
-    PciConfigAll *configSpace;
+    struct Params;
+    Params *_params;
 
-    /**
-     * A pointer to the object that contains the first 64 bytes of
-     * config space
-     */
-    PciConfigData *configData;
+  public:
+    struct Params
+    {
+        std::string name;
+        Platform *plat;
+        MemoryController *mmu;
+
+        /**
+         * A pointer to the configspace all object that calls us when
+         * a read comes to this particular device/function.
+         */
+        PciConfigAll *configSpace;
 
-    /** The bus number we are on */
-    uint32_t busNum;
+        /**
+         * A pointer to the object that contains the first 64 bytes of
+         * config space
+         */
+        PciConfigData *configData;
 
-    /** The device number we have */
-    uint32_t deviceNum;
+        /** The bus number we are on */
+        uint32_t busNum;
 
-    /** The function number */
-    uint32_t functionNum;
+        /** The device number we have */
+        uint32_t deviceNum;
 
-    /** The current config space. Unlike the PciConfigData this is updated
-     * during simulation while continues to refelect what was in the config file.
+        /** The function number */
+        uint32_t functionNum;
+    };
+    const Params *params() const { return _params; }
+
+  protected:
+    /** The current config space. Unlike the PciConfigData this is
+     * updated during simulation while continues to refelect what was
+     * in the config file.
      */
     PCIConfig config;
 
@@ -110,21 +125,29 @@ class PciDev : public DmaDevice
     /** The current address mapping of the BARs */
     Addr BARAddrs[6];
 
+  protected:
+    Platform *plat;
+    PciConfigData *configData;
+
+  public:
+    Addr pciToDma(Addr pciAddr) const
+    { return plat->pciToDma(pciAddr); }
+
+    void
+    intrPost()
+    { plat->postPciInt(configData->config.hdr.pci0.interruptLine); }
+
+    void
+    intrClear()
+    { plat->clearPciInt(configData->config.hdr.pci0.interruptLine); }
+
   public:
     /**
-     * Constructor for PCI Dev. This function copies data from the config file
-     * object PCIConfigData and registers the device with a PciConfigAll object.
-     * @param name name of the object
-     * @param mmu a pointer to the memory controller
-     * @param cf a pointer to the config space object that this device need to
-     *           register with
-     * @param cd A pointer to the config space values specified in the conig file
-     * @param bus the bus this device is on
-     * @param dev the device id of this device
-     * @param func the function number of this device
+     * Constructor for PCI Dev. This function copies data from the
+     * config file object PCIConfigData and registers the device with
+     * a PciConfigAll object.
      */
-    PciDev(const std::string &name, MemoryController *mmu, PciConfigAll *cf,
-           PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func);
+    PciDev(Params *params);
 
     virtual Fault read(MemReqPtr &req, uint8_t *data) {
         return No_Fault;
@@ -168,4 +191,4 @@ class PciDev : public DmaDevice
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 };
 
-#endif // __PCI_DEV_HH__
+#endif // __DEV_PCIDEV_HH__
diff --git a/dev/platform.cc b/dev/platform.cc
index 8515d543a..cf012352b 100644
--- a/dev/platform.cc
+++ b/dev/platform.cc
@@ -32,5 +32,23 @@
 
 using namespace std;
 
+void
+Platform::postPciInt(int line)
+{
+   panic("No PCI interrupt support in platform.");
+}
+
+void
+Platform::clearPciInt(int line)
+{
+   panic("No PCI interrupt support in platform.");
+}
+
+Addr
+Platform::pciToDma(Addr pciAddr) const
+{
+   panic("No PCI dma support in platform.");
+}
+
 DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)
 
diff --git a/dev/platform.hh b/dev/platform.hh
index 0c90e06ba..717e49411 100644
--- a/dev/platform.hh
+++ b/dev/platform.hh
@@ -35,6 +35,7 @@
 #define __PLATFORM_HH_
 
 #include "sim/sim_object.hh"
+#include "targetarch/isa_traits.hh"
 
 class PciConfigAll;
 class IntrControl;
@@ -65,8 +66,9 @@ class Platform : public SimObject
     virtual void postConsoleInt() = 0;
     virtual void clearConsoleInt() = 0;
     virtual Tick intrFrequency() = 0;
-    virtual void postPciInt(int line) = 0;
-    virtual void clearPciInt(int line) = 0;
+    virtual void postPciInt(int line);
+    virtual void clearPciInt(int line);
+    virtual Addr pciToDma(Addr pciAddr) const;
 };
 
 #endif // __PLATFORM_HH_
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index ce2d473a9..f98254354 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -77,13 +77,19 @@ Tsunami::clearConsoleInt()
 void
 Tsunami::postPciInt(int line)
 {
-   this->cchip->postDRIR(line);
+   cchip->postDRIR(line);
 }
 
 void
 Tsunami::clearPciInt(int line)
 {
-   this->cchip->clearDRIR(line);
+   cchip->clearDRIR(line);
+}
+
+Addr
+Tsunami::pciToDma(Addr pciAddr) const
+{
+    return pchip->translatePciToDma(pciAddr);
 }
 
 void
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 0a7fdbcd9..05563f80b 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -118,6 +118,8 @@ class Tsunami : public Platform
      */
     virtual void clearPciInt(int line);
 
+    virtual Addr pciToDma(Addr pciAddr) const;
+
   /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.