summaryrefslogtreecommitdiff
path: root/dev
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-02-27 11:44:35 -0500
committerKevin Lim <ktlim@umich.edu>2006-02-27 11:44:35 -0500
commit70b35bab5778799805fe9b6040b23eb1885dbfc3 (patch)
tree6fdddb98a8efac65667af903a24ecca528eee25a /dev
parent51647e7bec8e8607fc5713b4ace2c24ce8a7455a (diff)
downloadgem5-70b35bab5778799805fe9b6040b23eb1885dbfc3.tar.xz
Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC. Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future). arch/alpha/alpha_memory.cc: Change accesses to IPR to go through the XC. arch/alpha/ev5.cc: Change accesses for IPRs to go through the misc regs. arch/alpha/isa/decoder.isa: Change accesses to IPRs to go through the misc regs. readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect(). arch/alpha/isa/fp.isa: Change accesses to IPRs and Fpcr to go through the misc regs. arch/alpha/isa/main.isa: Add support for all misc regs being accessed through readMiscReg() and setMiscReg(). Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index. arch/alpha/isa_traits.hh: Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs. Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect. The latter are basically the original read/write IPR functions, while the former are normal reads/writes. The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs. arch/alpha/stacktrace.cc: cpu/simple/cpu.cc: dev/sinic.cc: Change accesses to the IPRs to go through the XC. arch/alpha/vtophys.cc: Change access to the IPR to go through the XC. arch/isa_parser.py: Change generation of code for control registers to use the readMiscReg and setMiscReg functions. base/remote_gdb.cc: Change accesses to the IPR to go through the XC. cpu/exec_context.hh: Use the miscRegs to access the lock addr, lock flag, and other misc registers. cpu/o3/alpha_cpu.hh: cpu/simple/cpu.hh: Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions. cpu/o3/alpha_cpu_impl.hh: Change accesses to the IPRs to go through the miscRegs. For now comment out some of the accesses to the misc regs until the proxy exec context is completed. cpu/o3/alpha_dyn_inst.hh: Change accesses to misc regs to use readMiscReg and setMiscReg. cpu/o3/alpha_dyn_inst_impl.hh: Remove old misc reg accessors. cpu/o3/cpu.cc: Comment out old misc reg accesses until the proxy exec context is completed. cpu/o3/cpu.hh: Change accesses to the misc regs. cpu/o3/regfile.hh: Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg. They are dummy functions for now until the proxy exec context is completed. kern/kernel_stats.cc: kern/system_events.cc: Have accesses to the IPRs go through the XC. kern/tru64/tru64.hh: Have accesses to the misc regs use the new access methods. --HG-- extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
Diffstat (limited to 'dev')
-rw-r--r--dev/sinic.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/dev/sinic.cc b/dev/sinic.cc
index c499d2f49..84f5c70df 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -376,7 +376,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
+ int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
@@ -472,7 +472,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
+ int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;