Since the delayed write stuff is gone, get rid of regWrite

and merge it with writeBar0

--HG--
extra : convert_revision : 354642e0d528b6a5a7f2cdf0264d93e738b2d4eb

2 files changed, 6 insertions, 18 deletions

diff --git a/dev/sinic.cc b/dev/sinic.cc
index c499d2f49..a9363954b 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -489,30 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
         panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
               info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
 
-    //uint32_t reg32 = *(uint32_t *)data;
+    uint32_t reg32 = *(uint32_t *)data;
     uint64_t reg64 = *(uint64_t *)data;
+    VirtualReg &vnic = virtualRegs[index];
+
     DPRINTF(EthernetPIO,
             "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
-            info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr,
+            info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
             req->paddr, req->vaddr, req->size);
 
     prepareWrite(cpu, index);
 
-    regWrite(daddr, cpu, data);
-
-    return NoFault;
-}
-
-void
-Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
-{
-    Addr index = daddr >> Regs::VirtualShift;
-    Addr raddr = daddr & Regs::VirtualMask;
-
-    uint32_t reg32 = *(uint32_t *)data;
-    uint64_t reg64 = *(uint64_t *)data;
-    VirtualReg &vnic = virtualRegs[index];
-
     switch (raddr) {
       case Regs::Config:
         changeConfig(reg32);
@@ -559,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
         }
         break;
     }
+
+    return NoFault;
 }
 
 void
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 97ebf4c30..c4027be86 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -280,7 +280,6 @@ class Device : public Base
     Fault iprRead(Addr daddr, int cpu, uint64_t &result);
     Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
     Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    void regWrite(Addr daddr, int cpu, const uint8_t *data);
     Tick cacheAccess(MemReqPtr &req);
 
 /**