Merge ktlim@zizzer.eecs.umich.edu:/bk/m5

into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22

6 files changed, 32 insertions, 10 deletions

diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 857cdeb78..ae044427e 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -97,7 +97,8 @@ IdeController::IdeController(Params *p)
 
         dmaInterface = new DMAInterface<Bus>(name() + ".dma",
                                              params()->host_bus,
-                                             params()->host_bus, 1);
+                                             params()->host_bus, 1,
+                                             true);
         pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
     }
 
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 47631642c..0b416750f 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -120,11 +120,13 @@ NSGigE::NSGigE(Params *p)
         if (p->payload_bus)
             dmaInterface = new DMAInterface<Bus>(name() + ".dma",
                                                  p->header_bus,
-                                                 p->payload_bus, 1);
+                                                 p->payload_bus, 1,
+                                                 p->dma_no_allocate);
         else
             dmaInterface = new DMAInterface<Bus>(name() + ".dma",
                                                  p->header_bus,
-                                                 p->header_bus, 1);
+                                                 p->header_bus, 1,
+                                                 p->dma_no_allocate);
     } else if (p->payload_bus) {
         pioInterface = newPioInterface(name(), p->hier,
                                        p->payload_bus, this,
@@ -134,7 +136,8 @@ NSGigE::NSGigE(Params *p)
 
         dmaInterface = new DMAInterface<Bus>(name() + ".dma",
                                              p->payload_bus,
-                                             p->payload_bus, 1);
+                                             p->payload_bus, 1,
+                                             p->dma_no_allocate);
     }
 
 
@@ -747,6 +750,10 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
                 reg = regs.tesr;
                 break;
 
+              case M5REG:
+                reg = params()->m5reg;
+                break;
+
               default:
                 panic("reading unimplemented register: addr=%#x", daddr);
             }
@@ -2708,6 +2715,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
     Param<uint32_t> pci_func;
     Param<uint32_t> tx_fifo_size;
     Param<uint32_t> rx_fifo_size;
+    Param<uint32_t> m5reg;
+    Param<bool> dma_no_allocate;
 
 END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -2740,7 +2749,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
     INIT_PARAM(pci_dev, "PCI device number"),
     INIT_PARAM(pci_func, "PCI function code"),
     INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072),
-    INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072)
+    INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072),
+    INIT_PARAM(m5reg, "m5 register"),
+    INIT_PARAM_DFLT(dma_no_allocate, "Should DMA reads allocate cache lines", true)
 
 END_INIT_SIM_OBJECT_PARAMS(NSGigE)
 
@@ -2777,6 +2788,8 @@ CREATE_SIM_OBJECT(NSGigE)
     params->eaddr = hardware_address;
     params->tx_fifo_size = tx_fifo_size;
     params->rx_fifo_size = rx_fifo_size;
+    params->m5reg = m5reg;
+    params->dma_no_allocate = dma_no_allocate;
     return new NSGigE(params);
 }
 
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 544a300c3..cbb7185e7 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -343,6 +343,8 @@ class NSGigE : public PciDev
         Net::EthAddr eaddr;
         uint32_t tx_fifo_size;
         uint32_t rx_fifo_size;
+        uint32_t m5reg;
+        bool dma_no_allocate;
     };
 
     NSGigE(Params *params);
diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h
index 01577fa39..ab9833788 100644
--- a/dev/ns_gige_reg.h
+++ b/dev/ns_gige_reg.h
@@ -117,7 +117,8 @@
 #define TANLPAR		0xec
 #define TANER		0xf0
 #define TESR		0xf4
-#define LAST            0xf4
+#define M5REG		0xf8
+#define LAST            0xf8
 #define RESERVED        0xfc
 
 /* chip command register */
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 9535a58ca..4d6ecf668 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -103,11 +103,11 @@ Device::Device(Params *p)
         if (p->payload_bus)
             dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
                                                  p->header_bus, p->payload_bus,
-                                                 1);
+                                                 1, p->dma_no_allocate);
         else
             dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
                                                  p->header_bus, p->header_bus,
-                                                 1);
+                                                 1, p->dma_no_allocate);
     } else if (p->payload_bus) {
         pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
                                        &Device::cacheAccess);
@@ -115,7 +115,8 @@ Device::Device(Params *p)
         pioLatency = p->pio_latency * p->payload_bus->clockRatio;
 
         dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
-                                             p->payload_bus, 1);
+                                             p->payload_bus, 1,
+                                             p->dma_no_allocate);
     }
 }
 
@@ -1388,6 +1389,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
     Param<Tick> dma_read_factor;
     Param<Tick> dma_write_delay;
     Param<Tick> dma_write_factor;
+    Param<bool> dma_no_allocate;
 
 END_DECLARE_SIM_OBJECT_PARAMS(Device)
 
@@ -1421,7 +1423,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
     INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),
     INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0),
     INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0),
-    INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0)
+    INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
+    INIT_PARAM_DFLT(dma_no_allocate, "Should we allocat on read in cache", true)
 
 END_INIT_SIM_OBJECT_PARAMS(Device)
 
@@ -1458,6 +1461,7 @@ CREATE_SIM_OBJECT(Device)
     params->dma_read_factor = dma_read_factor;
     params->dma_write_delay = dma_write_delay;
     params->dma_write_factor = dma_write_factor;
+    params->dma_no_allocate = dma_no_allocate;
     return new Device(params);
 }
 
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 6597357a2..062a5408b 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -316,6 +316,7 @@ class Device : public Base
         Tick dma_read_factor;
         Tick dma_write_delay;
         Tick dma_write_factor;
+        bool dma_no_allocate;
     };
 
   protected: