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| author | Benjamin Nash <benash@umich.edu> | 2005-08-16 15:45:30 -0400 |
|---|---|---|
| committer | Benjamin Nash <benash@umich.edu> | 2005-08-16 15:45:30 -0400 |
| commit | 979d609656c8ab5e8345e21c401fa542e0138168 (patch) | |
| tree | b0cfedf1f452a9c673d2d39ded416e21f09e5d36 /dev | |
| parent | 0d82e0f8b6d44bc759c3cd7d1e4d499fbbdc459e (diff) | |
| parent | 1906abcde04c7f9af8186ac1a8a726a9ea80936f (diff) | |
| download | gem5-979d609656c8ab5e8345e21c401fa542e0138168.tar.xz | |
Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_dir/m5
into zed.eecs.umich.edu:/z/benash/bk/m5
--HG--
extra : convert_revision : 9b7ca872187a13179118ad0651301d531332dc63
Diffstat (limited to 'dev')
| -rw-r--r-- | dev/uart8250.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/dev/uart8250.cc b/dev/uart8250.cc index bbde14769..2ad020462 100644 --- a/dev/uart8250.cc +++ b/dev/uart8250.cc @@ -147,13 +147,15 @@ Uart8250::read(MemReqPtr &req, uint8_t *data) case 0x2: // Intr Identification Register (IIR) DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status); - //Tx interrupts are cleared on IIR reads - status &= ~TX_INT; - - if (status & RX_INT) + if (status & RX_INT) /* Rx data interrupt has a higher priority */ *(uint8_t*)data = IIR_RXID; + else if (status & TX_INT) + *(uint8_t*)data = IIR_TXID; else *(uint8_t*)data = IIR_NOPEND; + + //Tx interrupts are cleared on IIR reads + status &= ~TX_INT; break; case 0x3: // Line Control Register (LCR) *(uint8_t*)data = LCR; |