Slowly on our way to booting with Tsunami

--HG--
extra : convert_revision : ec8e7e2dc929ad84c5e320fbfb02070e94cd1ad1

5 files changed, 504 insertions, 0 deletions

diff --git a/dev/tsunami.cc b/dev/tsunami.cc
new file mode 100644
index 000000000..4024db884
--- /dev/null
+++ b/dev/tsunami.cc
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "cpu/intr_control.hh"
+#include "dev/console.hh"
+#include "dev/etherdev.hh"
+#include "dev/scsi_ctrl.hh"
+#include "dev/tlaser_clock.hh"
+#include "dev/tsunami_cchip.hh"
+#include "dev/tsunami.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+
+Tsunami::Tsunami(const string &name, ScsiController *s, EtherDev *e,
+                       TlaserClock *c, TsunamiCChip *cc, SimConsole *con,
+               IntrControl *ic, int intr_freq)
+    : SimObject(name), intctrl(ic), cons(con), scsi(s), ethernet(e),
+      clock(c), cchip(cc), interrupt_frequency(intr_freq)
+{
+    for (int i = 0; i < Tsunami::Max_CPUs; i++)
+        intr_sum_type[i] = 0;
+}
+
+void
+Tsunami::serialize(std::ostream &os)
+{
+    SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
+}
+
+void
+Tsunami::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
+
+    SimObjectParam<ScsiController *> scsi;
+    SimObjectParam<EtherDev *> ethernet;
+    SimObjectParam<TlaserClock *> clock;
+    SimObjectParam<TsunamiCChip *> cchip;
+    SimObjectParam<SimConsole *> cons;
+    SimObjectParam<IntrControl *> intrctrl;
+    Param<int> interrupt_frequency;
+
+END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
+
+    INIT_PARAM(scsi, "scsi controller"),
+    INIT_PARAM(ethernet, "ethernet controller"),
+    INIT_PARAM(clock, "turbolaser clock"),
+    INIT_PARAM(cchip, "cchip"),
+    INIT_PARAM(cons, "system console"),
+    INIT_PARAM(intrctrl, "interrupt controller"),
+    INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1200)
+
+END_INIT_SIM_OBJECT_PARAMS(Tsunami)
+
+
+CREATE_SIM_OBJECT(Tsunami)
+{
+    return new Tsunami(getInstanceName(), scsi, ethernet, clock,
+                           cchip, cons, intrctrl, interrupt_frequency);
+}
+
+REGISTER_SIM_OBJECT("Tsunami", Tsunami)
+
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
new file mode 100644
index 000000000..f4f108d43
--- /dev/null
+++ b/dev/tsunami.hh
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __TSUNAMI_HH__
+#define __TSUNAMI_HH__
+
+#include "sim/sim_object.hh"
+
+class IntrControl;
+class ConsoleListener;
+class SimConsole;
+class ScsiController;
+class TlaserClock;
+class EtherDev;
+class TsunamiCChip;
+
+class Tsunami : public SimObject
+{
+  public:
+
+    static const int Max_CPUs = 4;
+
+    IntrControl *intctrl;
+//    ConsoleListener *listener;
+    SimConsole *cons;
+
+    ScsiController *scsi;
+    EtherDev *ethernet;
+
+    TlaserClock *clock;
+    TsunamiCChip *cchip;
+
+    int intr_sum_type[Tsunami::Max_CPUs];
+    int ipi_pending[Tsunami::Max_CPUs];
+
+    int interrupt_frequency;
+
+  public:
+    Tsunami(const std::string &name, ScsiController *scsi,
+               EtherDev *ethernet, TlaserClock *clock, TsunamiCChip *tc,
+               SimConsole *, IntrControl *intctrl,
+               int intrFreq);
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+#endif // __TSUNAMI_HH__
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
new file mode 100644
index 000000000..364d0fac2
--- /dev/null
+++ b/dev/tsunami_cchip.cc
@@ -0,0 +1,236 @@
+/* $Id$ */
+
+/* @file
+ * Tsunami CChip (processor, memory, or IO)
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "base/trace.hh"
+#include "cpu/exec_context.hh"
+#include "dev/console.hh"
+#include "dev/etherdev.hh"
+#include "dev/scsi_ctrl.hh"
+#include "dev/tlaser_clock.hh"
+#include "dev/tsunami_cchip.hh"
+#include "dev/tsunamireg.h"
+#include "dev/tsunami.hh"
+#include "mem/functional_mem/memory_control.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+
+TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
+                       Addr addr, Addr mask, MemoryController *mmu)
+    : MmapDevice(name, addr, mask, mmu), tsunami(t)
+{
+    for(int i=0; i < Tsunami::Max_CPUs; i++) {
+        dim[i] = 0;
+        dir[i] = 0;
+    }
+
+    drir = 0;
+}
+
+Fault
+TsunamiCChip::read(MemReqPtr req, uint8_t *data)
+{
+    DPRINTF(Tsunami, "cchip read  va=%#x size=%d\n",
+            req->vaddr, req->size);
+
+    Addr daddr = (req->paddr & addr_mask) >> 6;
+//    ExecContext *xc = req->xc;
+//    int cpuid = xc->cpu_id;
+
+    switch (req->size) {
+
+      case sizeof(uint64_t):
+          switch(daddr) {
+              case TSDEV_CC_CSR:
+                  *(uint64_t*)data = 0x0;
+                  return No_Fault;
+              case TSDEV_CC_MTR:
+                  panic("TSDEV_CC_MTR not implemeted\n");
+                   return No_Fault;
+              case TSDEV_CC_MISC:
+                  panic("TSDEV_CC_MISC not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_AAR0:
+              case TSDEV_CC_AAR1:
+              case TSDEV_CC_AAR2:
+              case TSDEV_CC_AAR3:
+                  panic("TSDEV_CC_AARx not implemeted\n");
+                  return No_Fault;
+              case TSDEV_CC_DIM0:
+                  *(uint64_t*)data = dim[0];
+                  return No_Fault;
+              case TSDEV_CC_DIM1:
+                  *(uint64_t*)data = dim[1];
+                  return No_Fault;
+              case TSDEV_CC_DIM2:
+                  *(uint64_t*)data = dim[2];
+                  return No_Fault;
+              case TSDEV_CC_DIM3:
+                  *(uint64_t*)data = dim[3];
+                  return No_Fault;
+              case TSDEV_CC_DIR0:
+                  *(uint64_t*)data = dir[0];
+                  return No_Fault;
+              case TSDEV_CC_DIR1:
+                  *(uint64_t*)data = dir[1];
+                  return No_Fault;
+              case TSDEV_CC_DIR2:
+                  *(uint64_t*)data = dir[2];
+                  return No_Fault;
+              case TSDEV_CC_DIR3:
+                  *(uint64_t*)data = dir[3];
+                  return No_Fault;
+              case TSDEV_CC_DRIR:
+                  *(uint64_t*)data = drir;
+                  return No_Fault;
+              case TSDEV_CC_PRBEN:
+                  panic("TSDEV_CC_PRBEN not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_IIC0:
+              case TSDEV_CC_IIC1:
+              case TSDEV_CC_IIC2:
+              case TSDEV_CC_IIC3:
+                  panic("TSDEV_CC_IICx not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_MPR0:
+              case TSDEV_CC_MPR1:
+              case TSDEV_CC_MPR2:
+              case TSDEV_CC_MPR3:
+                  panic("TSDEV_CC_MPRx not implemented\n");
+                  return No_Fault;
+           } // uint64_t
+
+      break;
+      case sizeof(uint32_t):
+      case sizeof(uint16_t):
+      case sizeof(uint8_t):
+      default:
+        panic("invalid access size(?) for tsunami register!");
+    }
+    DPRINTFN("Tsunami CChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
+
+    return No_Fault;
+}
+
+Fault
+TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
+{
+    DPRINTF(Tsunami, "Tsunami CChip write - va=%#x size=%d \n",
+            req->vaddr, req->size);
+
+    Addr daddr = (req->paddr & addr_mask) >> 6;
+
+    switch (req->size) {
+
+      case sizeof(uint64_t):
+          switch(daddr) {
+              case TSDEV_CC_CSR:
+                  panic("TSDEV_CC_CSR write\n");
+                  return No_Fault;
+              case TSDEV_CC_MTR:
+                  panic("TSDEV_CC_MTR write not implemented\n");
+                   return No_Fault;
+              case TSDEV_CC_MISC:
+                  panic("TSDEV_CC_MISC write not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_AAR0:
+              case TSDEV_CC_AAR1:
+              case TSDEV_CC_AAR2:
+              case TSDEV_CC_AAR3:
+                  panic("TSDEV_CC_AARx write not implemeted\n");
+                  return No_Fault;
+              case TSDEV_CC_DIM0:
+                   dim[0] = *(uint64_t*)data;
+                  return No_Fault;
+              case TSDEV_CC_DIM1:
+                  dim[1] = *(uint64_t*)data;
+                  return No_Fault;
+              case TSDEV_CC_DIM2:
+                  dim[2] = *(uint64_t*)data;
+                  return No_Fault;
+              case TSDEV_CC_DIM3:
+                  dim[3] = *(uint64_t*)data;
+                  return No_Fault;
+              case TSDEV_CC_DIR0:
+              case TSDEV_CC_DIR1:
+              case TSDEV_CC_DIR2:
+              case TSDEV_CC_DIR3:
+                  panic("TSDEV_CC_DIR write not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_DRIR:
+                  panic("TSDEV_CC_DRIR write not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_PRBEN:
+                  panic("TSDEV_CC_PRBEN write not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_IIC0:
+              case TSDEV_CC_IIC1:
+              case TSDEV_CC_IIC2:
+              case TSDEV_CC_IIC3:
+                  panic("TSDEV_CC_IICx write not implemented\n");
+                  return No_Fault;
+              case TSDEV_CC_MPR0:
+              case TSDEV_CC_MPR1:
+              case TSDEV_CC_MPR2:
+              case TSDEV_CC_MPR3:
+                  panic("TSDEV_CC_MPRx write not implemented\n");
+                  return No_Fault;
+          }
+
+      break;
+      case sizeof(uint32_t):
+      case sizeof(uint16_t):
+      case sizeof(uint8_t):
+      default:
+        panic("invalid access size(?) for tsunami register!");
+    }
+
+    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
+
+    return No_Fault;
+}
+
+void
+TsunamiCChip::serialize(std::ostream &os)
+{
+    // code should be written
+}
+
+void
+TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
+{
+    //code should be written
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+    SimObjectParam<Tsunami *> tsunami;
+    SimObjectParam<MemoryController *> mmu;
+    Param<Addr> addr;
+    Param<Addr> mask;
+
+END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+    INIT_PARAM(tsunami, "Tsunami"),
+    INIT_PARAM(mmu, "Memory Controller"),
+    INIT_PARAM(addr, "Device Address"),
+    INIT_PARAM(mask, "Address Mask")
+
+END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
+
+CREATE_SIM_OBJECT(TsunamiCChip)
+{
+    return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
+}
+
+REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
new file mode 100644
index 000000000..4fbe36ee9
--- /dev/null
+++ b/dev/tsunami_cchip.hh
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* @file
+ * Turbolaser system bus node (processor, memory, or IO)
+ */
+
+#ifndef __TSUNAMI_CCHIP_HH__
+#define __TSUNAMI_CCHIP_HH__
+
+#include "mem/functional_mem/mmap_device.hh"
+#include "dev/tsunami.hh"
+
+/*
+ * Tsunami CChip
+ */
+class TsunamiCChip : public MmapDevice
+{
+  public:
+
+  protected:
+    Tsunami *tsunami;
+    uint64_t dim[Tsunami::Max_CPUs];
+    uint64_t dir[Tsunami::Max_CPUs];
+    uint64_t drir;
+
+  public:
+    TsunamiCChip(const std::string &name, Tsunami *t,
+               Addr addr, Addr mask, MemoryController *mmu);
+
+    virtual Fault read(MemReqPtr req, uint8_t *data);
+    virtual Fault write(MemReqPtr req, const uint8_t *data);
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+#endif // __TSUNAMI_CCHIP_HH__
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h
new file mode 100644
index 000000000..fe92846c2
--- /dev/null
+++ b/dev/tsunamireg.h
@@ -0,0 +1,33 @@
+
+#ifndef __TSUNAMIREG_H__
+#define __TSUNAMIREG_H__
+
+#define TSDEV_CC_CSR    0x00
+#define TSDEV_CC_MTR    0x01
+#define TSDEV_CC_MISC   0x02
+
+#define TSDEV_CC_AAR0   0x04
+#define TSDEV_CC_AAR1   0x05
+#define TSDEV_CC_AAR2   0x06
+#define TSDEV_CC_AAR3   0x07
+#define TSDEV_CC_DIM0   0x08
+#define TSDEV_CC_DIM1   0x09
+#define TSDEV_CC_DIR0   0x0A
+#define TSDEV_CC_DIR1   0x0B
+#define TSDEV_CC_DRIR   0x0C
+#define TSDEV_CC_PRBEN  0x0D
+#define TSDEV_CC_IIC0   0x0E
+#define TSDEV_CC_IIC1   0x0F
+#define TSDEV_CC_MPR0   0x10
+#define TSDEV_CC_MPR1   0x11
+#define TSDEV_CC_MPR2   0x12
+#define TSDEV_CC_MPR3   0x13
+
+#define TSDEV_CC_DIM2   0x18
+#define TSDEV_CC_DIM3   0x19
+#define TSDEV_CC_DIR2   0x1A
+#define TSDEV_CC_DIR3   0x1B
+#define TSDEV_CC_IIC2   0x1C
+#define TSDEV_CC_IIC3   0x1D
+
+#endif // __TSUNAMIREG_H__