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authorLisa Hsu <hsul@eecs.umich.edu>2004-06-12 14:24:20 -0400
committerLisa Hsu <hsul@eecs.umich.edu>2004-06-12 14:24:20 -0400
commitbfcb0882813272bc8ef74b98ed53e28a36147bb8 (patch)
tree343df40d79b90d5fd4d428c46ff50f74d9a3adb0 /dev
parentf0f96233e8a5e805c3ac7dbc47eba2bffff264a7 (diff)
downloadgem5-bfcb0882813272bc8ef74b98ed53e28a36147bb8.tar.xz
minor mods for mimicking NS83820 functionality
dev/ide_ctrl.cc: generalize these #defs dev/ide_ctrl.hh: put these in pcireg.h dev/ns_gige.cc: do i need io_enable? and assert will fail if i actually need to implement it, which may give clue as to wehtehr i need to implmeent the mem_enable and bm_enable stuff. dev/ns_gige.hh: implement this in case it's needed dev/pcireg.h: put these defs in pcireg instead --HG-- extra : convert_revision : 5e3581b5da17410f943907139bd479f15d2231e8
Diffstat (limited to 'dev')
-rw-r--r--dev/ide_ctrl.cc4
-rw-r--r--dev/ide_ctrl.hh4
-rw-r--r--dev/ns_gige.cc32
-rw-r--r--dev/ns_gige.hh7
-rw-r--r--dev/pcireg.h5
5 files changed, 45 insertions, 7 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 67da63a9b..68e7e58ad 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -342,12 +342,12 @@ IdeController::WriteConfig(int offset, int size, uint32_t data)
// (like updating the PIO ranges)
switch (offset) {
case PCI_COMMAND:
- if (config.data[offset] & IOSE)
+ if (config.data[offset] & PCI_CMD_IOSE)
io_enabled = true;
else
io_enabled = false;
- if (config.data[offset] & BME)
+ if (config.data[offset] & PCI_CMD_BME)
bm_enabled = true;
else
bm_enabled = false;
diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index 9418c8895..679c7422b 100644
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -74,10 +74,6 @@
#define UDMACTL (5)
#define UDMATIM (6)
-// PCI Command bit fields
-#define BME 0x04 // Bus master function enable
-#define IOSE 0x01 // I/O space enable
-
typedef enum RegType {
COMMAND_BLOCK = 0,
CONTROL_BLOCK,
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index ce35222b9..28181ba64 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -98,7 +98,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
uint32_t func, bool rx_filter, const int eaddr[6])
- : PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t),
+ : PciDev(name, mmu, cf, cd, bus, dev, func), tsunami(t), io_enable(false),
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
txXferLen(0), rxXferLen(0), txPktXmitted(0), txState(txIdle), CTDD(false),
txFifoCnt(0), txFifoAvail(MAX_TX_FIFO_SIZE), txHalt(false),
@@ -242,6 +242,28 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
// Need to catch writes to BARs to update the PIO interface
switch (offset) {
+ //seems to work fine without all these, but i ut in the IO to
+ //double check, an assertion will fail if we need to properly
+ // imlpement it
+ case PCI_COMMAND:
+ if (config.data[offset] & PCI_CMD_IOSE)
+ io_enable = true;
+ else
+ io_enable = false;
+#if 0
+ if (config.data[offset] & PCI_CMD_BME)
+ bm_enabled = true;
+ else
+ bm_enabled = false;
+ break;
+
+ if (config.data[offset] & PCI_CMD_MSE)
+ mem_enable = true;
+ else
+ mem_enable = false;
+ break;
+#endif
+
case PCI0_BASE_ADDR0:
if (BARAddrs[0] != 0) {
@@ -272,6 +294,8 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
Fault
NSGigE::read(MemReqPtr &req, uint8_t *data)
{
+ assert(io_enable);
+
//The mask is to give you only the offset into the device register file
Addr daddr = req->paddr & 0xfff;
DPRINTF(EthernetPIO, "read da=%#x pa=%#x va=%#x size=%d\n",
@@ -474,6 +498,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
Fault
NSGigE::write(MemReqPtr &req, const uint8_t *data)
{
+ assert(io_enable);
+
Addr daddr = req->paddr & 0xfff;
DPRINTF(EthernetPIO, "write da=%#x pa=%#x va=%#x size=%d\n",
daddr, req->paddr, req->vaddr, req->size);
@@ -2085,6 +2111,8 @@ NSGigE::serialize(ostream &os)
SERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
+ SERIALIZE_SCALAR(io_enable);
+
/*
* Serialize the data Fifos
*/
@@ -2242,6 +2270,8 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(rom.perfectMatch, EADDR_LEN);
+ UNSERIALIZE_SCALAR(io_enable);
+
/*
* unserialize the data fifos
*/
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 31068e3d8..25a7781e5 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -158,6 +158,13 @@ class NSGigE : public PciDev
dp_regs regs;
dp_rom rom;
+ /** pci settings */
+ bool io_enable;
+#if 0
+ bool mem_enable;
+ bool bm_enable;
+#endif
+
/*** BASIC STRUCTURES FOR TX/RX ***/
/* Data FIFOs */
pktbuf_t txFifo;
diff --git a/dev/pcireg.h b/dev/pcireg.h
index 96924a6a9..8e8b7b451 100644
--- a/dev/pcireg.h
+++ b/dev/pcireg.h
@@ -114,6 +114,11 @@ union PCIConfig {
#define PCI_HEADER_TYPE 0x0E // Header Type ro
#define PCI_BIST 0x0F // Built in self test rw
+// some pci command reg bitfields
+#define PCI_CMD_BME 0x04 // Bus master function enable
+#define PCI_CMD_MSE 0x02 // Memory Space Access enable
+#define PCI_CMD_IOSE 0x01 // I/O space enable
+
// Type 0 PCI offsets
#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw