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authorAli Saidi <saidi@eecs.umich.edu>2004-01-22 00:08:48 -0500
committerAli Saidi <saidi@eecs.umich.edu>2004-01-22 00:08:48 -0500
commitde17a0330443dac568f99d4fabaef9b6a8dcff46 (patch)
treedc914d07e4cc1f97de26661d20f00d2037cbb0bc /dev
parent0e805e1ff35a5c70f8aff785db709c1f3b8d0c28 (diff)
downloadgem5-de17a0330443dac568f99d4fabaef9b6a8dcff46.tar.xz
updated tsunami_dma
dev/tsunami_dma.cc: decide actually differentiating between the different i/o requests would be a better idea dev/tsunami_dma.hh: added mask and mode variables, incase they are needed dev/tsunamireg.h: added some i/o port defs --HG-- extra : convert_revision : 5c7a88a8f8c8725359737b399cfa80610149a5f4
Diffstat (limited to 'dev')
-rw-r--r--dev/tsunami_dma.cc38
-rw-r--r--dev/tsunami_dma.hh5
-rw-r--r--dev/tsunamireg.h10
3 files changed, 51 insertions, 2 deletions
diff --git a/dev/tsunami_dma.cc b/dev/tsunami_dma.cc
index d52cf2b8f..4b1dca74c 100644
--- a/dev/tsunami_dma.cc
+++ b/dev/tsunami_dma.cc
@@ -39,7 +39,8 @@ TsunamiDMA::read(MemReqPtr req, uint8_t *data)
// Addr daddr = (req->paddr & addr_mask) >> 6;
// ExecContext *xc = req->xc;
// int cpuid = xc->cpu_id;
- *(uint64_t*)data = 0x00;
+ panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
+ // *(uint64_t*)data = 0x00;
return No_Fault;
}
@@ -50,7 +51,40 @@ TsunamiDMA::write(MemReqPtr req, const uint8_t *data)
DPRINTF(Tsunami, "dma write - va=%#x size=%d IOPort=%#x\n",
req->vaddr, req->size, req->vaddr & 0xfff);
- //Addr daddr = (req->paddr & addr_mask) >> 6;
+ Addr daddr = (req->paddr & addr_mask);
+
+ switch(req->size) {
+ case sizeof(uint8_t):
+ switch(daddr) {
+ case TSDEV_PIC1_MASK:
+ mask1 = *(uint8_t*)data;
+ return No_Fault;
+ case TSDEV_PIC2_MASK:
+ mask2 = *(uint8_t*)data;
+ return No_Fault;
+ case TSDEV_DMA1_RESET:
+ return No_Fault;
+ case TSDEV_DMA2_RESET:
+ return No_Fault;
+ case TSDEV_DMA1_MODE:
+ mode1 = *(uint8_t*)data;
+ return No_Fault;
+ case TSDEV_DMA2_MODE:
+ mode2 = *(uint8_t*)data;
+ return No_Fault;
+ case TSDEV_DMA1_MASK:
+ case TSDEV_DMA2_MASK:
+ return No_Fault;
+ default:
+ panic("I/O Write - va%#x size %d\n", req->vaddr, req->size);
+ }
+ case sizeof(uint16_t):
+ case sizeof(uint32_t):
+ case sizeof(uint64_t):
+ default:
+ panic("I/O Write - invalid size - va %#x size %d\n", req->vaddr, req->size);
+ }
+
return No_Fault;
}
diff --git a/dev/tsunami_dma.hh b/dev/tsunami_dma.hh
index 4daa6946d..f23abce2d 100644
--- a/dev/tsunami_dma.hh
+++ b/dev/tsunami_dma.hh
@@ -45,6 +45,11 @@ class TsunamiDMA : public MmapDevice
protected:
+ uint8_t mask1;
+ uint8_t mask2;
+ uint8_t mode1;
+ uint8_t mode2;
+
public:
TsunamiDMA(const std::string &name, /*Tsunami *t,*/
Addr addr, Addr mask, MemoryController *mmu);
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h
index 12275fee2..b41b3994d 100644
--- a/dev/tsunamireg.h
+++ b/dev/tsunamireg.h
@@ -65,4 +65,14 @@
#define TSDEV_DC_DREV 0x22
#define TSDEV_DC_DSC2 0x23
+// I/O Ports
+#define TSDEV_PIC1_MASK 0x21
+#define TSDEV_PIC2_MASK 0xA1
+#define TSDEV_DMA1_RESET 0x0D
+#define TSDEV_DMA2_RESET 0xDA
+#define TSDEV_DMA1_MODE 0x0B
+#define TSDEV_DMA2_MODE 0xD6
+#define TSDEV_DMA1_MASK 0x0A
+#define TSDEV_DMA2_MASK 0xD4
+
#endif // __TSUNAMIREG_H__