diff options
| author | Nathan Binkert <binkertn@umich.edu> | 2005-04-24 21:32:32 -0400 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2005-04-24 21:32:32 -0400 |
| commit | 3154e2a0c75d6e95458d86b30c982efc003c1f68 (patch) | |
| tree | da13a3d29c4be79aea25b8a42e2df500df835ea5 /dev | |
| parent | 6f9dba3cec9fd638c274dc0dc7ebfb4f2db74883 (diff) | |
| download | gem5-3154e2a0c75d6e95458d86b30c982efc003c1f68.tar.xz | |
Add the m5 parameter to the ns83820 device model so that we
can pass simulator specific options to the device driver.
dev/ns_gige.cc:
Add the m5 register and parameter to the ns83820 device model
so that we can pass simulator specific options to the device
driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
Add the m5 register to the ns83820 device model
--HG--
extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
Diffstat (limited to 'dev')
| -rw-r--r-- | dev/ns_gige.cc | 9 | ||||
| -rw-r--r-- | dev/ns_gige.hh | 1 | ||||
| -rw-r--r-- | dev/ns_gige_reg.h | 3 |
3 files changed, 11 insertions, 2 deletions
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 47631642c..7560b1994 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -747,6 +747,10 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) reg = regs.tesr; break; + case M5REG: + reg = params()->m5reg; + break; + default: panic("reading unimplemented register: addr=%#x", daddr); } @@ -2708,6 +2712,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param<uint32_t> pci_func; Param<uint32_t> tx_fifo_size; Param<uint32_t> rx_fifo_size; + Param<uint32_t> m5reg; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -2740,7 +2745,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(pci_dev, "PCI device number"), INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM_DFLT(tx_fifo_size, "max size in bytes of txFifo", 131072), - INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072) + INIT_PARAM_DFLT(rx_fifo_size, "max size in bytes of rxFifo", 131072), + INIT_PARAM(m5reg, "m5 register") END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -2777,6 +2783,7 @@ CREATE_SIM_OBJECT(NSGigE) params->eaddr = hardware_address; params->tx_fifo_size = tx_fifo_size; params->rx_fifo_size = rx_fifo_size; + params->m5reg = m5reg; return new NSGigE(params); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 544a300c3..357f08253 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -343,6 +343,7 @@ class NSGigE : public PciDev Net::EthAddr eaddr; uint32_t tx_fifo_size; uint32_t rx_fifo_size; + uint32_t m5reg; }; NSGigE(Params *params); diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index 01577fa39..ab9833788 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -117,7 +117,8 @@ #define TANLPAR 0xec #define TANER 0xf0 #define TESR 0xf4 -#define LAST 0xf4 +#define M5REG 0xf8 +#define LAST 0xf8 #define RESERVED 0xfc /* chip command register */ |