Add support for "serializing" instructions that flush

execution pipeline (Alpha trapb & excb).

Add support for write memory barriers (mostly impacts
store buffer).

Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.

arch/alpha/isa_desc:
    Implement trapb, excb, mb, and wmb as insts with
    no execution effect (empty execute() function) but
    with flags that indicate their side effects.

    Also make sure every instruction that needs to go to
    the execute stage has a real opClass value, since we
    are now using No_OpClass to signal insts that can get
    dropped at dispatch.

    StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
    Add flags to indicate serializing insts (trapb, excb) and
    memory and write barriers.

    Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
    Make name() return value const.

--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c

1 files changed, 1 insertions, 1 deletions

diff --git a/dev/etherlink.hh b/dev/etherlink.hh
index 895bac2e1..e1a7957ee 100644
--- a/dev/etherlink.hh
+++ b/dev/etherlink.hh
@@ -89,7 +89,7 @@ class EtherLink : public SimObject
         Link(const std::string &name, double rate, EtherDump *dump);
         ~Link() {}
 
-        virtual std::string name() const { return objName; }
+        virtual const std::string name() const { return objName; }
 
         bool busy() const { return (bool)packet; }
         bool transmit(PacketPtr &packet);