Add support for all devices to get requests from a timing memory bus.

In the future, this can be used for actual data, but for now, it's
so that devices can respond to timing accesses properly.  This way,
an uncached access on a bus further away will take longer to respond.

dev/alpha_console.cc:
dev/alpha_console.hh:
    suport the separate IO bus

--HG--
extra : convert_revision : ececb70f5febfd00231f6e406f93b2a79be01261

4 files changed, 142 insertions, 8 deletions

diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 2dc939b97..85b4d57f2 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -43,6 +43,9 @@
 #include "dev/console.hh"
 #include "dev/simple_disk.hh"
 #include "dev/tlaser_clock.hh"
+#include "mem/bus/bus.hh"
+#include "mem/bus/pio_interface.hh"
+#include "mem/bus/pio_interface_impl.hh"
 #include "mem/functional_mem/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
@@ -51,11 +54,18 @@ using namespace std;
 
 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
                            System *system, BaseCPU *cpu, TlaserClock *clock,
-                           int num_cpus, MemoryController *mmu, Addr a)
-    : FunctionalMemory(name), disk(d), console(cons), addr(a)
+                           int num_cpus, MemoryController *mmu, Addr a,
+                           HierParams *hier, Bus *bus)
+    : PioDevice(name), disk(d), console(cons), addr(a)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
 
+    if (bus) {
+        pioInterface = newPioInterface(name, hier, bus, this,
+                                       &AlphaConsole::cacheAccess);
+        pioInterface->setAddrRange(addr, addr + size);
+    }
+
     consoleData = new uint8_t[size];
     memset(consoleData, 0, size);
 
@@ -183,6 +193,12 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
     return No_Fault;
 }
 
+Tick
+AlphaConsole::cacheAccess(MemReqPtr &req)
+{
+    return curTick + 1000;
+}
+
 void
 AlphaAccess::serialize(ostream &os)
 {
@@ -251,6 +267,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
     SimObjectParam<System *> system;
     SimObjectParam<BaseCPU *> cpu;
     SimObjectParam<TlaserClock *> clock;
+    SimObjectParam<Bus*> io_bus;
+    SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 
@@ -263,14 +281,17 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu, "Processor"),
-    INIT_PARAM(clock, "Turbolaser Clock")
+    INIT_PARAM(clock, "Turbolaser Clock"),
+    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 
 CREATE_SIM_OBJECT(AlphaConsole)
 {
-    return  new AlphaConsole(getInstanceName(), sim_console, disk,
-                             system, cpu, clock, num_cpus, mmu, addr);
+    return new AlphaConsole(getInstanceName(), sim_console, disk,
+                            system, cpu, clock, num_cpus, mmu,
+                            addr, hier, io_bus);
 }
 
 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index 54a2af6d5..b617b64e7 100644
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -35,7 +35,7 @@
 
 #include "base/range.hh"
 #include "dev/alpha_access.h"
-#include "mem/functional_mem/functional_memory.hh"
+#include "dev/io_device.hh"
 #include "sim/host.hh"
 
 class BaseCPU;
@@ -69,7 +69,7 @@ class SimpleDisk;
  * primarily used doing boot before the kernel has loaded its device
  * drivers.
  */
-class AlphaConsole : public FunctionalMemory
+class AlphaConsole : public PioDevice
 {
   protected:
     union {
@@ -90,7 +90,8 @@ class AlphaConsole : public FunctionalMemory
     /** Standard Constructor */
     AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
                  System *system, BaseCPU *cpu, TlaserClock *clock,
-                 int num_cpus, MemoryController *mmu, Addr addr);
+                 int num_cpus, MemoryController *mmu, Addr addr,
+                 HierParams *hier, Bus *bus);
 
     /**
      * memory mapped reads and writes
@@ -103,6 +104,9 @@ class AlphaConsole : public FunctionalMemory
      */
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+  public:
+    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __ALPHA_CONSOLE_HH__
diff --git a/dev/io_device.cc b/dev/io_device.cc
new file mode 100644
index 000000000..65a18aec6
--- /dev/null
+++ b/dev/io_device.cc
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dev/io_device.hh"
+#include "mem/bus/base_interface.hh"
+
+PioDevice::PioDevice(const std::string &name)
+    : FunctionalMemory(name), pioInterface(NULL)
+{}
+
+PioDevice::~PioDevice()
+{
+    if (pioInterface)
+        delete pioInterface;
+}
+
+DmaDevice::DmaDevice(const std::string &name)
+    : PioDevice(name), dmaInterface(NULL)
+{}
+
+DmaDevice::~DmaDevice()
+{
+    if (dmaInterface)
+        delete dmaInterface;
+}
+
diff --git a/dev/io_device.hh b/dev/io_device.hh
new file mode 100644
index 000000000..39e6fa4aa
--- /dev/null
+++ b/dev/io_device.hh
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IO_DEVICE_HH__
+#define __IO_DEVICE_HH__
+
+#include "mem/functional_mem/functional_memory.hh"
+
+class BaseInterface;
+class Bus;
+class HierParams;
+
+class PioDevice : public FunctionalMemory
+{
+  protected:
+    BaseInterface *pioInterface;
+
+  public:
+    PioDevice(const std::string &name);
+    virtual ~PioDevice();
+};
+
+class DmaDevice : public PioDevice
+{
+  protected:
+    BaseInterface *dmaInterface;
+
+  public:
+    DmaDevice(const std::string &name);
+    virtual ~DmaDevice();
+};
+
+#endif // __IO_DEVICE_HH__