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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:54 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:54 -0500 |
commit | 88e2963951860966dd850ef874e5fed99fe78b88 (patch) | |
tree | 5c8ebbe7b69ec49ebbd762fd84c5bbf73a864bb3 /ext/drampower/src/MemPowerSpec.cc | |
parent | 407737614ed2431d75314eba813edfec40e95bcc (diff) | |
download | gem5-88e2963951860966dd850ef874e5fed99fe78b88.tar.xz |
mem: Fix cache MSHR conflict determination
This patch fixes a rather subtle issue in the sending of MSHR requests
in the cache, where the logic previously did not check for conflicts
between the MSRH queue and the write queue when requests were not
ready. The correct thing to do is to always check, since not having a
ready MSHR does not guarantee that there is no conflict.
The underlying problem seems to have slipped past due to the symmetric
timings used for the write queue and MSHR queue. However, with the
recent timing changes the bug caused regressions to fail.
Diffstat (limited to 'ext/drampower/src/MemPowerSpec.cc')
0 files changed, 0 insertions, 0 deletions