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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 15:02:23 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 15:02:23 -0500 |
commit | e8ed7b1d1b5bef31e9874f679a5797c2e00d06f1 (patch) | |
tree | 421c9c50377aa664958685914f5504c4c019e21f /ext/dsent/model/timing_graph/ElectricalTimingOptimizer.cc | |
parent | a098fad174d8559037602b248b8e6f7f46bfebbb (diff) | |
download | gem5-e8ed7b1d1b5bef31e9874f679a5797c2e00d06f1.tar.xz |
ext: add the source code for DSENT
This patch adds a tool called DSENT to the ext/ directory. DSENT
is a tool that models power and area for on-chip networks. The next
patch adds a script for using the tool.
Diffstat (limited to 'ext/dsent/model/timing_graph/ElectricalTimingOptimizer.cc')
-rw-r--r-- | ext/dsent/model/timing_graph/ElectricalTimingOptimizer.cc | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/ext/dsent/model/timing_graph/ElectricalTimingOptimizer.cc b/ext/dsent/model/timing_graph/ElectricalTimingOptimizer.cc new file mode 100644 index 000000000..dd7b4330a --- /dev/null +++ b/ext/dsent/model/timing_graph/ElectricalTimingOptimizer.cc @@ -0,0 +1,73 @@ +#include "model/timing_graph/ElectricalTimingOptimizer.h" + +#include "model/PortInfo.h" +#include "model/ModelGen.h" +#include "model/std_cells/StdCell.h" +#include "model/std_cells/StdCellLib.h" +#include "model/timing_graph/ElectricalNet.h" +#include "model/timing_graph/ElectricalTimingTree.h" + +namespace DSENT +{ + ElectricalTimingOptimizer::ElectricalTimingOptimizer(const String& instance_name_, const TechModel* tech_model_) + : ElectricalModel(instance_name_, tech_model_), m_model_(NULL) + {} + + ElectricalTimingOptimizer::~ElectricalTimingOptimizer() + {} + + void ElectricalTimingOptimizer::setModel(ElectricalModel* model_) + { + m_model_ = model_; + return; + } + + ElectricalModel* ElectricalTimingOptimizer::getModel() + { + return m_model_; + } + + void ElectricalTimingOptimizer::constructModel() + { + if(getModel() == NULL) + { + return; + } + + const Map<PortInfo*>* port_info = getModel()->getInputs(); + Map<PortInfo*>::ConstIterator it_begin = port_info->begin(); + Map<PortInfo*>::ConstIterator it_end = port_info->end(); + Map<PortInfo*>::ConstIterator it; + + for(it = it_begin; it != it_end; ++it) + { + const String& port_name = it->first; + const PortInfo* port_info = it->second; + StdCell* inv0 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver0"); + inv0->construct(); + StdCell* inv1 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver1"); + inv1->construct(); + + addSubInstances(inv0, 1.0); + addSubInstances(inv1, 1.0); + + createInputPort(port_name, port_info->getNetIndex()); + createNet(port_name + "Driver0In"); + createNet(port_name + "Driver0Out"); + createNet(port_name + "Driver1Out"); + assignVirtualFanin(port_name + "Driver0In", port_name); + portConnect(inv0, "A", port_name + "Driver0In"); + portConnect(inv0, "Y", port_name + "Driver0Out"); + portConnect(inv1, "A", port_name + "Driver0Out"); + portConnect(inv1, "Y", port_name + "Driver1Out"); + + createNet(port_name + "In", port_info->getNetIndex()); + assignVirtualFanout(port_name + "In", port_name + "Driver1Out"); + + portConnect(getModel(), port_name, port_name + "In"); + } + + return; + } +}// namespace DSENT + |