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author | Andreas Hansson <andreas.hansson@arm.com> | 2016-03-17 09:51:18 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-03-17 09:51:18 -0400 |
commit | 041ea8107e4250a9c120a6fde11f3dc415c2fe6a (patch) | |
tree | 13c75f78d88ab7c9077babd5e9b8a3a36fcba3d7 /ext/dsent/tech/TechModel.cc | |
parent | f5d1dd75e57d9c63c5f6ab4d0c7c0c45f8726a95 (diff) | |
download | gem5-041ea8107e4250a9c120a6fde11f3dc415c2fe6a.tar.xz |
mem: Create a separate class for the cache write buffer
This patch breaks out the cache write buffer into a separate class,
without affecting any stats. The goal of the patch is to avoid
encumbering the much-simpler write queue with the complex MSHR
handling. In a follow on patch this simplification allows us to
implement write combining.
The WriteQueue gets its own class, but shares a common ancestor, the
generic Queue, with the MSHRQueue.
Diffstat (limited to 'ext/dsent/tech/TechModel.cc')
0 files changed, 0 insertions, 0 deletions