ext: McPAT interface changes and fixes

This patch includes software engineering changes and some generic bug fixes
Joel Hestness and Yasuko Eckert made to McPAT 0.8. There are still known
issues/concernts we did not have a chance to address in this patch.

High-level changes in this patch include:
 1) Making XML parsing modular and hierarchical:
   - Shift parsing responsibility into the components
   - Read XML in a (mostly) context-free recursive manner so that McPAT input
     files can contain arbitrary component hierarchies
 2) Making power, energy, and area calculations a hierarchical and recursive
    process
   - Components track their subcomponents and recursively call compute
     functions in stages
   - Make C++ object hierarchy reflect inheritance of classes of components
     with similar structures
   - Simplify computeArea() and computeEnergy() functions to eliminate
     successive calls to calculate separate TDP vs. runtime energy
   - Remove Processor component (now unnecessary) and introduce a more abstract
     System component
 3) Standardizing McPAT output across all components
   - Use a single, common data structure for storing and printing McPAT output
   - Recursively call print functions through component hierarchy
 4) For caches, allow splitting data array and tag array reads and writes for
    better accuracy
 5) Improving the usability of CACTI by printing more helpful warning and error
    messages
 6) Minor: Impose more rigorous code style for clarity (more work still to be
    done)
Overall, these changes greatly reduce the amount of replicated code, and they
improve McPAT runtime and decrease memory footprint.

1 files changed, 127 insertions, 133 deletions

diff --git a/ext/mcpat/cacti/decoder.h b/ext/mcpat/cacti/decoder.h
index 35631e84b..a2ddf722c 100644
--- a/ext/mcpat/cacti/decoder.h
+++ b/ext/mcpat/cacti/decoder.h
@@ -2,6 +2,7 @@
  *                                McPAT/CACTI
  *                      SOFTWARE LICENSE AGREEMENT
  *            Copyright 2012 Hewlett-Packard Development Company, L.P.
+ *            Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
  *                          All Rights Reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,7 +26,7 @@
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ***************************************************************************/
 
@@ -42,9 +43,8 @@
 using namespace std;
 
 
-class Decoder : public Component
-{
-  public:
+class Decoder : public Component {
+public:
     Decoder(
         int _num_dec_signals,
         bool flag_way_select,
@@ -80,125 +80,120 @@ class Decoder : public Component
 
 
 
-class PredecBlk : public Component
-{
- public:
-  PredecBlk(
-      int num_dec_signals,
-      Decoder * dec,
-      double C_wire_predec_blk_out,
-      double R_wire_predec_blk_out,
-      int    num_dec_per_predec,
-      bool   is_dram_,
-      bool   is_blk1);
-
-  Decoder * dec;
-  bool exist;
-  int number_input_addr_bits;
-  double C_ld_predec_blk_out;
-  double R_wire_predec_blk_out;
-  int branch_effort_nand2_gate_output;
-  int branch_effort_nand3_gate_output;
-  bool   flag_two_unique_paths;
-  int flag_L2_gate;
-  int number_inputs_L1_gate;
-  int number_gates_L1_nand2_path;
-  int number_gates_L1_nand3_path;
-  int number_gates_L2;
-  int min_number_gates_L1;
-  int min_number_gates_L2;
-  int num_L1_active_nand2_path;
-  int num_L1_active_nand3_path;
-  double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
-  double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
-  double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
-  double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
-  double w_L2_n[MAX_NUMBER_GATES_STAGE];
-  double w_L2_p[MAX_NUMBER_GATES_STAGE];
-  double delay_nand2_path;
-  double delay_nand3_path;
-  powerDef power_nand2_path;
-  powerDef power_nand3_path;
-  powerDef power_L2;
-
-  bool is_dram_;
-
-  void compute_widths();
-  void compute_area();
-
-  void leakage_feedback(double temperature);
-
-  pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
-  // return <outrise_nand2, outrise_nand3>
+class PredecBlk : public Component {
+public:
+    PredecBlk(
+        int num_dec_signals,
+        Decoder * dec,
+        double C_wire_predec_blk_out,
+        double R_wire_predec_blk_out,
+        int    num_dec_per_predec,
+        bool   is_dram_,
+        bool   is_blk1);
+
+    Decoder * dec;
+    bool exist;
+    int number_input_addr_bits;
+    double C_ld_predec_blk_out;
+    double R_wire_predec_blk_out;
+    int branch_effort_nand2_gate_output;
+    int branch_effort_nand3_gate_output;
+    bool   flag_two_unique_paths;
+    int flag_L2_gate;
+    int number_inputs_L1_gate;
+    int number_gates_L1_nand2_path;
+    int number_gates_L1_nand3_path;
+    int number_gates_L2;
+    int min_number_gates_L1;
+    int min_number_gates_L2;
+    int num_L1_active_nand2_path;
+    int num_L1_active_nand3_path;
+    double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
+    double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
+    double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
+    double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
+    double w_L2_n[MAX_NUMBER_GATES_STAGE];
+    double w_L2_p[MAX_NUMBER_GATES_STAGE];
+    double delay_nand2_path;
+    double delay_nand3_path;
+    powerDef power_nand2_path;
+    powerDef power_nand3_path;
+    powerDef power_L2;
+
+    bool is_dram_;
+
+    void compute_widths();
+    void compute_area();
+
+    void leakage_feedback(double temperature);
+
+    pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
+    // return <outrise_nand2, outrise_nand3>
 };
 
 
-class PredecBlkDrv : public Component
-{
- public:
-  PredecBlkDrv(
-      int   way_select,
-      PredecBlk * blk_,
-      bool  is_dram);
-
-  int flag_driver_exists;
-  int number_input_addr_bits;
-  int number_gates_nand2_path;
-  int number_gates_nand3_path;
-  int min_number_gates;
-  int num_buffers_driving_1_nand2_load;
-  int num_buffers_driving_2_nand2_load;
-  int num_buffers_driving_4_nand2_load;
-  int num_buffers_driving_2_nand3_load;
-  int num_buffers_driving_8_nand3_load;
-  int num_buffers_nand3_path;
-  double c_load_nand2_path_out;
-  double c_load_nand3_path_out;
-  double r_load_nand2_path_out;
-  double r_load_nand3_path_out;
-  double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
-  double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
-  double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
-  double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
-  double delay_nand2_path;
-  double delay_nand3_path;
-  powerDef power_nand2_path;
-  powerDef power_nand3_path;
-
-  PredecBlk * blk;
-  Decoder   * dec;
-  bool  is_dram_;
-  int   way_select;
-
-  void compute_widths();
-  void compute_area();
-
-  void leakage_feedback(double temperature);
-
-
-  pair<double, double> compute_delays(
-      double inrisetime_nand2_path,
-      double inrisetime_nand3_path);  // return <outrise_nand2, outrise_nand3>
-
-  inline int num_addr_bits_nand2_path()
-  {
-    return num_buffers_driving_1_nand2_load +
-           num_buffers_driving_2_nand2_load +
-           num_buffers_driving_4_nand2_load;
-  }
-  inline int num_addr_bits_nand3_path()
-  {
-    return num_buffers_driving_2_nand3_load +
-           num_buffers_driving_8_nand3_load;
-  }
-  double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
+class PredecBlkDrv : public Component {
+public:
+    PredecBlkDrv(
+        int   way_select,
+        PredecBlk * blk_,
+        bool  is_dram);
+
+    int flag_driver_exists;
+    int number_input_addr_bits;
+    int number_gates_nand2_path;
+    int number_gates_nand3_path;
+    int min_number_gates;
+    int num_buffers_driving_1_nand2_load;
+    int num_buffers_driving_2_nand2_load;
+    int num_buffers_driving_4_nand2_load;
+    int num_buffers_driving_2_nand3_load;
+    int num_buffers_driving_8_nand3_load;
+    int num_buffers_nand3_path;
+    double c_load_nand2_path_out;
+    double c_load_nand3_path_out;
+    double r_load_nand2_path_out;
+    double r_load_nand3_path_out;
+    double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
+    double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
+    double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
+    double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
+    double delay_nand2_path;
+    double delay_nand3_path;
+    powerDef power_nand2_path;
+    powerDef power_nand3_path;
+
+    PredecBlk * blk;
+    Decoder   * dec;
+    bool  is_dram_;
+    int   way_select;
+
+    void compute_widths();
+    void compute_area();
+
+    void leakage_feedback(double temperature);
+
+
+    pair<double, double> compute_delays(
+        double inrisetime_nand2_path,
+        double inrisetime_nand3_path);  // return <outrise_nand2, outrise_nand3>
+
+    inline int num_addr_bits_nand2_path() {
+        return num_buffers_driving_1_nand2_load +
+               num_buffers_driving_2_nand2_load +
+               num_buffers_driving_4_nand2_load;
+    }
+    inline int num_addr_bits_nand3_path() {
+        return num_buffers_driving_2_nand3_load +
+               num_buffers_driving_8_nand3_load;
+    }
+    double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
 };
 
 
 
-class Predec : public Component
-{
-  public:
+class Predec : public Component {
+public:
     Predec(
         PredecBlkDrv * drv1,
         PredecBlkDrv * drv2);
@@ -214,7 +209,7 @@ class Predec : public Component
     powerDef block_power;
     powerDef driver_power;
 
-  private:
+private:
     // returns <delay, risetime>
     pair<double, double> get_max_delay_before_decoder(
         pair<double, double> input_pair1,
@@ -223,24 +218,23 @@ class Predec : public Component
 
 
 
-class Driver : public Component
-{
- public:
-  Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
+class Driver : public Component {
+public:
+    Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
 
-  int    number_gates;
-  int    min_number_gates;
-  double width_n[MAX_NUMBER_GATES_STAGE];
-  double width_p[MAX_NUMBER_GATES_STAGE];
-  double c_gate_load;
-  double c_wire_load;
-  double r_wire_load;
-  double delay;
-  powerDef power;
-  bool   is_dram_;
+    int    number_gates;
+    int    min_number_gates;
+    double width_n[MAX_NUMBER_GATES_STAGE];
+    double width_p[MAX_NUMBER_GATES_STAGE];
+    double c_gate_load;
+    double c_wire_load;
+    double r_wire_load;
+    double delay;
+    powerDef power;
+    bool   is_dram_;
 
-  void   compute_widths();
-  double compute_delay(double inrisetime);
+    void   compute_widths();
+    double compute_delay(double inrisetime);
 };