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| author | Yasuko Eckert <yasuko.eckert@amd.com> | 2014-06-04 07:48:20 -0700 |
|---|---|---|
| committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2014-06-04 07:48:20 -0700 |
| commit | fbe3688de3bd0438cb52ea1871be0d3e4cceed39 (patch) | |
| tree | 00cc1f98952b88c296a281e41c92384cd14ff344 /ext/mcpat/regression/test-8/power_region0.xml | |
| parent | 0deef376d96bfe0a3a2496714ac22471d9ee818a (diff) | |
| download | gem5-fbe3688de3bd0438cb52ea1871be0d3e4cceed39.tar.xz | |
ext: Add a McPAT regression tester
Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko
Eckert modified them to reflect the new McPAT interface and other changes
the previous patch made.
Diffstat (limited to 'ext/mcpat/regression/test-8/power_region0.xml')
| -rw-r--r-- | ext/mcpat/regression/test-8/power_region0.xml | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/ext/mcpat/regression/test-8/power_region0.xml b/ext/mcpat/regression/test-8/power_region0.xml new file mode 100644 index 000000000..13b895d7c --- /dev/null +++ b/ext/mcpat/regression/test-8/power_region0.xml @@ -0,0 +1,64 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1700"/> + <param name="temperature" value="380"/> + <param name="interconnect_projection_type" value="1"/> + <param name="device_type" value="0"/> + <param name="longer_channel_device" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="36"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="15"/> + <component id="system.tol2bus" name="bus" type="BusInterconnect"> + <param name="clockrate" value="1700"/> + <param name="link_throughput" value="1"/> + <param name="link_latency" value="1"/> + <param name="total_nodes" value="2"/> + <param name="input_ports" value="2"/> + <param name="output_ports" value="2"/> + <param name="global_linked_ports" value="1"/> + <param name="flit_bits" value="256"/> + <param name="chip_coverage" value="1"/> + <param name="pipelinable" value="1"/> + <param name="link_routing_over_percentage" value="0.5"/> + <param name="virtual_channel_per_port" value="1"/> + <param name="M_traffic_pattern" value="1"/> + <param name="link_len" value="1"/> + <param name="link_base_width" value="1"/> + <param name="link_base_height" value="1"/> + <param name="link_start_wiring_level" value="3"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <stat name="total_accesses" value="5"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> +</component> |