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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-30 11:34:44 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-05 08:44:51 +0000 |
commit | fd1a8bed393a2ef48d584fcabeee4d98eda0e3fa (patch) | |
tree | 833b58843b355645555f8df027b085f52f946c22 /ext/testlib/fixture.py | |
parent | 6b94fbb3ddb6e3b75c2499e3bd3e7d7400069133 (diff) | |
download | gem5-fd1a8bed393a2ef48d584fcabeee4d98eda0e3fa.tar.xz |
arch-arm: Rewrite MSR immediate instruction class
MSR <pstatefield>, #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:
* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).
This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)
Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'ext/testlib/fixture.py')
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