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| author | Richard Strong <rstrong@hp.com> | 2008-08-18 10:50:58 -0700 |
|---|---|---|
| committer | Richard Strong <rstrong@hp.com> | 2008-08-18 10:50:58 -0700 |
| commit | 8d018aef0f9de7129a77172a4164f36b2b093be6 (patch) | |
| tree | ff3d46df0e6c495ab95454e69607993ff45fe14f /ext | |
| parent | 6248e12704275bf4cc88f1743bb3a4bff7adcf9f (diff) | |
| download | gem5-8d018aef0f9de7129a77172a4164f36b2b093be6.tar.xz | |
Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
Diffstat (limited to 'ext')
0 files changed, 0 insertions, 0 deletions