Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.

They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76

3 files changed, 5 insertions, 5 deletions

diff --git a/kern/kernel_stats.cc b/kern/kernel_stats.cc
index 50bbaee00..3beeaa14a 100644
--- a/kern/kernel_stats.cc
+++ b/kern/kernel_stats.cc
@@ -240,7 +240,7 @@ Statistics::swpipl(int ipl)
 void
 Statistics::mode(cpu_mode newmode)
 {
-    Addr pcbb = xc->regs.ipr[AlphaISA::IPR_PALtemp23];
+    Addr pcbb = xc->readMiscReg(AlphaISA::IPR_PALtemp23);
 
     if ((newmode == kernel || newmode == interrupt) &&
             pcbb == idleProcess)
diff --git a/kern/system_events.cc b/kern/system_events.cc
index 55595b9b6..91625e60a 100644
--- a/kern/system_events.cc
+++ b/kern/system_events.cc
@@ -67,7 +67,7 @@ FnEvent::process(ExecContext *xc)
 void
 IdleStartEvent::process(ExecContext *xc)
 {
-    xc->kernelStats->setIdleProcess(xc->regs.ipr[AlphaISA::IPR_PALtemp23]);
+    xc->kernelStats->setIdleProcess(xc->readMiscReg(AlphaISA::IPR_PALtemp23));
     remove();
 }
 
diff --git a/kern/tru64/tru64.hh b/kern/tru64/tru64.hh
index 1579a54d8..ad568cb0c 100644
--- a/kern/tru64/tru64.hh
+++ b/kern/tru64/tru64.hh
@@ -729,7 +729,7 @@ class Tru64 {
             regs->floatRegFile.q[i] = htog(sc->sc_fpregs[i]);
         }
 
-        regs->miscRegs.fpcr = htog(sc->sc_fpcr);
+        xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));
 
         return 0;
     }
@@ -889,7 +889,7 @@ class Tru64 {
             ssp->nxm_sysevent = htog(0);
 
             if (i == 0) {
-                uint64_t uniq = xc->regs.miscRegs.uniq;
+                uint64_t uniq = xc->readMiscReg(TheISA::Uniq_DepTag);
                 ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset));
                 ssp->nxm_u.nxm_active = htog(uniq | 1);
             }
@@ -924,7 +924,7 @@ class Tru64 {
         ec->regs.intRegFile[TheISA::ArgumentReg0] = gtoh(attrp->registers.a0);
         ec->regs.intRegFile[27/*t12*/] = gtoh(attrp->registers.pc);
         ec->regs.intRegFile[TheISA::StackPointerReg] = gtoh(attrp->registers.sp);
-        ec->regs.miscRegs.uniq = uniq_val;
+        ec->setMiscReg(TheISA::Uniq_DepTag, uniq_val);
 
         ec->regs.pc = gtoh(attrp->registers.pc);
         ec->regs.npc = gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst);