Split SimpleCPU into two different models, AtomicSimpleCPU and

TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132

1 files changed, 15 insertions, 6 deletions

diff --git a/mem/bus.cc b/mem/bus.cc
index acc941434..f84e38301 100644
--- a/mem/bus.cc
+++ b/mem/bus.cc
@@ -48,9 +48,16 @@ Bus::init()
 /** Function called by the port when the bus is recieving a Timing
  * transaction.*/
 bool
-Bus::recvTiming(Packet &pkt, int id)
+Bus::recvTiming(Packet &pkt)
 {
-    return findPort(pkt.addr, id)->sendTiming(pkt);
+    Port *port;
+    if (pkt.dest == Packet::Broadcast) {
+        port = findPort(pkt.addr, pkt.src);
+    } else {
+        assert(pkt.dest > 0 && pkt.dest < interfaces.size());
+        port = interfaces[pkt.dest];
+    }
+    return port->sendTiming(pkt);
 }
 
 Port *
@@ -82,17 +89,19 @@ Bus::findPort(Addr addr, int id)
 /** Function called by the port when the bus is recieving a Atomic
  * transaction.*/
 Tick
-Bus::recvAtomic(Packet &pkt, int id)
+Bus::recvAtomic(Packet &pkt)
 {
-    return findPort(pkt.addr, id)->sendAtomic(pkt);
+    assert(pkt.dest == Packet::Broadcast);
+    return findPort(pkt.addr, pkt.src)->sendAtomic(pkt);
 }
 
 /** Function called by the port when the bus is recieving a Functional
  * transaction.*/
 void
-Bus::recvFunctional(Packet &pkt, int id)
+Bus::recvFunctional(Packet &pkt)
 {
-    findPort(pkt.addr, id)->sendFunctional(pkt);
+    assert(pkt.dest == Packet::Broadcast);
+    findPort(pkt.addr, pkt.src)->sendFunctional(pkt);
 }
 
 /** Function called by the port when the bus is recieving a status change.*/