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authorAli Saidi <saidi@eecs.umich.edu>2006-03-25 18:31:20 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-25 18:31:20 -0500
commitb38f67d5b7ad9c2f5ff7580e20fb86c4a877589d (patch)
tree861137c79bf858c09f63d71b51494cc9c3b043a7 /mem/bus.hh
parenta70ce910f3303efe934c564817cc421369f51b36 (diff)
downloadgem5-b38f67d5b7ad9c2f5ff7580e20fb86c4a877589d.tar.xz
Implement a very very simple bus
requestTime -> time responseTime -> packet.time Make CPU and memory able to connect to the bus dev/io_device.cc: update for request and packet both having a time hand platform off to port for eventual selection of request modes dev/io_device.hh: update for request and packet both havig a time hand platform off to port for eventual selection of request modes mem/bus.hh: Add a device map struct that maps a range to a portId - Which needs work it theory it should be an interval tree - but it is a list and works fine right now Add a function called findPort which returns port for an addr range Add a deviceBlockSize function that really shouldn't exist, but it was easier than fixing the translating port mem/packet.hh: add a time to each packet mem/physical.cc: mem/physical.hh: python/m5/objects/PhysicalMemory.py: Make physical memory take a MemObject parameter of what to connect to mem/request.hh: remove requestTime/responseTime for just time in request which is requset time and the time in the packet which is responsetime python/m5/objects/BaseCPU.py: Instead of memory cpu connects to any memory object python/m5/objects/Bus.py: Fix for new bus object --HG-- extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
Diffstat (limited to 'mem/bus.hh')
-rw-r--r--mem/bus.hh24
1 files changed, 24 insertions, 0 deletions
diff --git a/mem/bus.hh b/mem/bus.hh
index e26065295..7790bdce3 100644
--- a/mem/bus.hh
+++ b/mem/bus.hh
@@ -45,6 +45,13 @@
class Bus : public MemObject
{
+ struct DevMap {
+ int portId;
+ Range<Addr> range;
+ };
+ std::vector<DevMap> portList;
+
+
/** Function called by the port when the bus is recieving a Timing
transaction.*/
bool recvTiming(Packet &pkt, int id);
@@ -60,6 +67,16 @@ class Bus : public MemObject
/** Function called by the port when the bus is recieving a status change.*/
void recvStatusChange(Port::Status status, int id);
+ /** Find which port connected to this bus (if any) should be given a packet
+ * with this address.
+ * @param addr Address to find port for.
+ * @param id Id of the port this packet was received from (to prevent
+ * loops)
+ * @return pointer to port that the packet should be sent out of.
+ */
+ Port *
+ Bus::findPort(Addr addr, int id);
+
/** Decleration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BusPort : public Port
@@ -104,6 +121,10 @@ class Bus : public MemObject
// the 'owned' address ranges of all the other interfaces on
// this bus...
virtual void addressRanges(AddrRangeList &range_list, bool &owner);
+
+ // Hack to make translating port work without changes
+ virtual int deviceBlockSize() { return 32; }
+
};
/** A count of the number of interfaces connected to this bus. */
@@ -123,6 +144,9 @@ class Bus : public MemObject
interfaces[id] = new BusPort(this, id);
return interfaces[id];
}
+ Bus(const std::string &n)
+ : MemObject(n) {}
+
};
#endif //__MEM_BUS_HH__