Move the port from base memory object into the physical memory object.

The Memory is now a pure virtual base class for all memory type objects (DRAM, physical).
We should consider renaming MemObject to something more meaningful to represent it is for all memory heirarchy objects, perhaps MemHeirObject?

mem/physical.cc:
mem/physical.hh:
    Move the port from the base class into the actual object.

--HG--
extra : convert_revision : b7754ee7b90fd8f816f9876dce374c1d43c7e34b

1 files changed, 82 insertions, 1 deletions

diff --git a/mem/physical.cc b/mem/physical.cc
index 4c1743293..e6d99358b 100644
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -90,7 +90,7 @@ PhysicalMemory::PhysicalMemory(const string &n, Range<Addr> range,
 #endif
 
 PhysicalMemory::PhysicalMemory(const string &n)
-    : Memory(n), base_addr(0), pmem_addr(NULL)
+    : Memory(n), memoryPort(this), base_addr(0), pmem_addr(NULL)
 {
     // Hardcoded to 128 MB for now.
     pmem_size = 1 << 27;
@@ -171,6 +171,86 @@ PhysicalMemory::deviceBlockSize()
     return 0;
 }
 
+bool
+PhysicalMemory::doTimingAccess (Packet &pkt)
+{
+    doFunctionalAccess(pkt);
+    //Schedule a response event at curTick + lat;
+    return true;
+}
+
+Tick
+PhysicalMemory::doAtomicAccess(Packet &pkt)
+{
+    doFunctionalAccess(pkt);
+    return curTick + lat;
+}
+
+void
+PhysicalMemory::doFunctionalAccess(Packet &pkt)
+{
+    switch (pkt.cmd) {
+      case Read:
+        prot_read(pkt.addr, (uint8_t *)pkt.data, pkt.size);
+
+      case Write:
+        prot_write(pkt.addr, (uint8_t *)pkt.data, pkt.size);
+
+      default:
+        panic("unimplemented");
+    }
+}
+
+Port *
+PhysicalMemory::getPort(const char *if_name)
+{
+    return &memoryPort;
+}
+
+void
+PhysicalMemory::recvStatusChange(Port::Status status)
+{
+    panic("??");
+}
+
+PhysicalMemory::MemoryPort::MemoryPort(PhysicalMemory *_memory)
+    : memory(_memory)
+{ }
+
+void
+PhysicalMemory::MemoryPort::recvStatusChange(Port::Status status)
+{
+    memory->recvStatusChange(status);
+}
+
+void
+PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
+                                           bool &owner)
+{
+    panic("??");
+}
+
+
+bool
+PhysicalMemory::MemoryPort::recvTiming(Packet &pkt)
+{
+    return memory->doTimingAccess(pkt);
+}
+
+Tick
+PhysicalMemory::MemoryPort::recvAtomic(Packet &pkt)
+{
+    return memory->doAtomicAccess(pkt);
+}
+
+void
+PhysicalMemory::MemoryPort::recvFunctional(Packet &pkt)
+{
+    memory->doFunctionalAccess(pkt);
+}
+
+
+
 void
 PhysicalMemory::serialize(ostream &os)
 {
@@ -278,6 +358,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
 
 }
 
+
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
 
     Param<string> file;